[oe-commits] org.oe.dev libaio: add 0.3.106 which build for ARM
hrw commit
openembedded-commits at lists.openembedded.org
Sat Oct 14 17:18:35 UTC 2006
libaio: add 0.3.106 which build for ARM
Author: hrw at openembedded.org
Branch: org.openembedded.dev
Revision: 208594a90e4ca1f56f7baeb97e372d73a4fdda65
ViewMTN: http://monotone.openembedded.org/revision.psp?id=208594a90e4ca1f56f7baeb97e372d73a4fdda65
Files:
1
packages/libaio/libaio-0.3.106
packages/libaio/libaio-0.3.106/00_arches.patch
packages/libaio/libaio-0.3.106/destdir.patch
packages/libaio/libaio-0.3.106/libaio_0.3.106-2.diff.gz
packages/libaio/libaio_0.3.106.bb
mtn:manual_merge
true
Diffs:
#
# mt diff -rd19521b45816b661206fef21cbcac6be4c118f2c -r208594a90e4ca1f56f7baeb97e372d73a4fdda65
#
#
#
# add_dir "packages/libaio/libaio-0.3.106"
#
# add_file "packages/libaio/libaio-0.3.106/00_arches.patch"
# content [cb7cae621aa8f597dedbb89fffc315c59c8dea58]
#
# add_file "packages/libaio/libaio-0.3.106/destdir.patch"
# content [80d195bd87d8d6f1c060130950b02df017a93f80]
#
# add_file "packages/libaio/libaio-0.3.106/libaio_0.3.106-2.diff.gz"
# content [296d914c7d75b2d1a4108abfe1d98b6185260f43]
#
# add_file "packages/libaio/libaio_0.3.106.bb"
# content [bc6b22d698d11158398eccf5f7c20acd9a6e7208]
#
# set "packages/libaio/libaio-0.3.106/libaio_0.3.106-2.diff.gz"
# attr "mtn:manual_merge"
# value "true"
#
============================================================
--- packages/libaio/libaio-0.3.106/00_arches.patch cb7cae621aa8f597dedbb89fffc315c59c8dea58
+++ packages/libaio/libaio-0.3.106/00_arches.patch cb7cae621aa8f597dedbb89fffc315c59c8dea58
@@ -0,0 +1,770 @@
+--- libaio-0.3.106.orig/src/syscall-m68k.h
++++ libaio-0.3.106/src/syscall-m68k.h
+@@ -0,0 +1,78 @@
++#define __NR_io_setup 241
++#define __NR_io_destroy 242
++#define __NR_io_getevents 243
++#define __NR_io_submit 244
++#define __NR_io_cancel 245
++
++#define io_syscall1(type,fname,sname,atype,a) \
++type fname(atype a) \
++{ \
++register long __res __asm__ ("%d0") = __NR_##sname; \
++register long __a __asm__ ("%d1") = (long)(a); \
++__asm__ __volatile__ ("trap #0" \
++ : "+d" (__res) \
++ : "d" (__a) ); \
++return (type) __res; \
++}
++
++#define io_syscall2(type,fname,sname,atype,a,btype,b) \
++type fname(atype a,btype b) \
++{ \
++register long __res __asm__ ("%d0") = __NR_##sname; \
++register long __a __asm__ ("%d1") = (long)(a); \
++register long __b __asm__ ("%d2") = (long)(b); \
++__asm__ __volatile__ ("trap #0" \
++ : "+d" (__res) \
++ : "d" (__a), "d" (__b) \
++ ); \
++return (type) __res; \
++}
++
++#define io_syscall3(type,fname,sname,atype,a,btype,b,ctype,c) \
++type fname(atype a,btype b,ctype c) \
++{ \
++register long __res __asm__ ("%d0") = __NR_##sname; \
++register long __a __asm__ ("%d1") = (long)(a); \
++register long __b __asm__ ("%d2") = (long)(b); \
++register long __c __asm__ ("%d3") = (long)(c); \
++__asm__ __volatile__ ("trap #0" \
++ : "+d" (__res) \
++ : "d" (__a), "d" (__b), \
++ "d" (__c) \
++ ); \
++return (type) __res; \
++}
++
++#define io_syscall4(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d) \
++type fname (atype a, btype b, ctype c, dtype d) \
++{ \
++register long __res __asm__ ("%d0") = __NR_##sname; \
++register long __a __asm__ ("%d1") = (long)(a); \
++register long __b __asm__ ("%d2") = (long)(b); \
++register long __c __asm__ ("%d3") = (long)(c); \
++register long __d __asm__ ("%d4") = (long)(d); \
++__asm__ __volatile__ ("trap #0" \
++ : "+d" (__res) \
++ : "d" (__a), "d" (__b), \
++ "d" (__c), "d" (__d) \
++ ); \
++return (type) __res; \
++}
++
++#define io_syscall5(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
++type fname (atype a,btype b,ctype c,dtype d,etype e) \
++{ \
++register long __res __asm__ ("%d0") = __NR_##sname; \
++register long __a __asm__ ("%d1") = (long)(a); \
++register long __b __asm__ ("%d2") = (long)(b); \
++register long __c __asm__ ("%d3") = (long)(c); \
++register long __d __asm__ ("%d4") = (long)(d); \
++register long __e __asm__ ("%d5") = (long)(e); \
++__asm__ __volatile__ ("trap #0" \
++ : "+d" (__res) \
++ : "d" (__a), "d" (__b), \
++ "d" (__c), "d" (__d), "d" (__e) \
++ ); \
++return (type) __res; \
++}
++
+--- libaio-0.3.106.orig/src/syscall-sparc.h
++++ libaio-0.3.106/src/syscall-sparc.h
+@@ -0,0 +1,130 @@
++/* $Id: unistd.h,v 1.74 2002/02/08 03:57:18 davem Exp $ */
++
++/*
++ * System calls under the Sparc.
++ *
++ * Don't be scared by the ugly clobbers, it is the only way I can
++ * think of right now to force the arguments into fixed registers
++ * before the trap into the system call with gcc 'asm' statements.
++ *
++ * Copyright (C) 1995 David S. Miller (davem at caip.rutgers.edu)
++ *
++ * SunOS compatibility based upon preliminary work which is:
++ *
++ * Copyright (C) 1995 Adrian M. Rodriguez (adrian at remus.rutgers.edu)
++ */
++
++
++#define __NR_io_setup 268
++#define __NR_io_destroy 269
++#define __NR_io_submit 270
++#define __NR_io_cancel 271
++#define __NR_io_getevents 272
++
++
++#define io_syscall1(type,fname,sname,type1,arg1) \
++type fname(type1 arg1) \
++{ \
++long __res; \
++register long __g1 __asm__ ("g1") = __NR_##sname; \
++register long __o0 __asm__ ("o0") = (long)(arg1); \
++__asm__ __volatile__ ("t 0x10\n\t" \
++ "bcc 1f\n\t" \
++ "mov %%o0, %0\n\t" \
++ "sub %%g0, %%o0, %0\n\t" \
++ "1:\n\t" \
++ : "=r" (__res), "=&r" (__o0) \
++ : "1" (__o0), "r" (__g1) \
++ : "cc"); \
++if (__res < -255 || __res >= 0) \
++ return (type) __res; \
++return -1; \
++}
++
++#define io_syscall2(type,fname,sname,type1,arg1,type2,arg2) \
++type fname(type1 arg1,type2 arg2) \
++{ \
++long __res; \
++register long __g1 __asm__ ("g1") = __NR_##sname; \
++register long __o0 __asm__ ("o0") = (long)(arg1); \
++register long __o1 __asm__ ("o1") = (long)(arg2); \
++__asm__ __volatile__ ("t 0x10\n\t" \
++ "bcc 1f\n\t" \
++ "mov %%o0, %0\n\t" \
++ "sub %%g0, %%o0, %0\n\t" \
++ "1:\n\t" \
++ : "=r" (__res), "=&r" (__o0) \
++ : "1" (__o0), "r" (__o1), "r" (__g1) \
++ : "cc"); \
++if (__res < -255 || __res >= 0) \
++ return (type) __res; \
++return -1; \
++}
++
++#define io_syscall3(type,fname,sname,type1,arg1,type2,arg2,type3,arg3) \
++type fname(type1 arg1,type2 arg2,type3 arg3) \
++{ \
++long __res; \
++register long __g1 __asm__ ("g1") = __NR_##sname; \
++register long __o0 __asm__ ("o0") = (long)(arg1); \
++register long __o1 __asm__ ("o1") = (long)(arg2); \
++register long __o2 __asm__ ("o2") = (long)(arg3); \
++__asm__ __volatile__ ("t 0x10\n\t" \
++ "bcc 1f\n\t" \
++ "mov %%o0, %0\n\t" \
++ "sub %%g0, %%o0, %0\n\t" \
++ "1:\n\t" \
++ : "=r" (__res), "=&r" (__o0) \
++ : "1" (__o0), "r" (__o1), "r" (__o2), "r" (__g1) \
++ : "cc"); \
++if (__res < -255 || __res>=0) \
++ return (type) __res; \
++return -1; \
++}
++
++#define io_syscall4(type,fname,sname,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
++type fname(type1 arg1, type2 arg2, type3 arg3, type4 arg4) \
++{ \
++long __res; \
++register long __g1 __asm__ ("g1") = __NR_##sname; \
++register long __o0 __asm__ ("o0") = (long)(arg1); \
++register long __o1 __asm__ ("o1") = (long)(arg2); \
++register long __o2 __asm__ ("o2") = (long)(arg3); \
++register long __o3 __asm__ ("o3") = (long)(arg4); \
++__asm__ __volatile__ ("t 0x10\n\t" \
++ "bcc 1f\n\t" \
++ "mov %%o0, %0\n\t" \
++ "sub %%g0, %%o0, %0\n\t" \
++ "1:\n\t" \
++ : "=r" (__res), "=&r" (__o0) \
++ : "1" (__o0), "r" (__o1), "r" (__o2), "r" (__o3), "r" (__g1) \
++ : "cc"); \
++if (__res < -255 || __res>=0) \
++ return (type) __res; \
++return -1; \
++}
++
++#define io_syscall5(type,fname,sname,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
++ type5,arg5) \
++type fname(type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \
++{ \
++long __res; \
++register long __g1 __asm__ ("g1") = __NR_##sname; \
++register long __o0 __asm__ ("o0") = (long)(arg1); \
++register long __o1 __asm__ ("o1") = (long)(arg2); \
++register long __o2 __asm__ ("o2") = (long)(arg3); \
++register long __o3 __asm__ ("o3") = (long)(arg4); \
++register long __o4 __asm__ ("o4") = (long)(arg5); \
++__asm__ __volatile__ ("t 0x10\n\t" \
++ "bcc 1f\n\t" \
++ "mov %%o0, %0\n\t" \
++ "sub %%g0, %%o0, %0\n\t" \
++ "1:\n\t" \
++ : "=r" (__res), "=&r" (__o0) \
++ : "1" (__o0), "r" (__o1), "r" (__o2), "r" (__o3), "r" (__o4), "r" (__g1) \
++ : "cc"); \
++if (__res < -255 || __res>=0) \
++ return (type) __res; \
++return -1; \
++}
++
+--- libaio-0.3.106.orig/src/syscall.h
++++ libaio-0.3.106/src/syscall.h
+@@ -22,6 +22,16 @@
+ #include "syscall-s390.h"
+ #elif defined(__alpha__)
+ #include "syscall-alpha.h"
++#elif defined(__arm__)
++#include "syscall-arm.h"
++#elif defined(__m68k__)
++#include "syscall-m68k.h"
++#elif defined(__sparc__)
++#include "syscall-sparc.h"
++#elif defined(__hppa__)
++#include "syscall-parisc.h"
++#elif defined(__mips__)
++#include "syscall-mips.h"
+ #else
+ #error "add syscall-arch.h"
+ #endif
+--- libaio-0.3.106.orig/src/syscall-mips.h
++++ libaio-0.3.106/src/syscall-mips.h
+@@ -0,0 +1,223 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle
++ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
++ *
++ * Changed system calls macros _syscall5 - _syscall7 to push args 5 to 7 onto
++ * the stack. Robin Farine for ACN S.A, Copyright (C) 1996 by ACN S.A
++ */
++
++#ifndef _MIPS_SIM_ABI32
++#define _MIPS_SIM_ABI32 1
++#define _MIPS_SIM_NABI32 2
++#define _MIPS_SIM_ABI64 3
++#endif
++
++#if _MIPS_SIM == _MIPS_SIM_ABI32
++
++/*
++ * Linux o32 style syscalls are in the range from 4000 to 4999.
++ */
++#define __NR_Linux 4000
++#define __NR_io_setup (__NR_Linux + 241)
++#define __NR_io_destroy (__NR_Linux + 242)
++#define __NR_io_getevents (__NR_Linux + 243)
++#define __NR_io_submit (__NR_Linux + 244)
++#define __NR_io_cancel (__NR_Linux + 245)
++
++#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
++
++#if _MIPS_SIM == _MIPS_SIM_ABI64
++
++/*
++ * Linux 64-bit syscalls are in the range from 5000 to 5999.
++ */
++#define __NR_Linux 5000
++#define __NR_io_setup (__NR_Linux + 200)
++#define __NR_io_destroy (__NR_Linux + 201)
++#define __NR_io_getevents (__NR_Linux + 202)
++#define __NR_io_submit (__NR_Linux + 203)
++#define __NR_io_cancel (__NR_Linux + 204)
++#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
++
++#if _MIPS_SIM == _MIPS_SIM_NABI32
++
++/*
++ * Linux N32 syscalls are in the range from 6000 to 6999.
++ */
++#define __NR_Linux 6000
++#define __NR_io_setup (__NR_Linux + 200)
++#define __NR_io_destroy (__NR_Linux + 201)
++#define __NR_io_getevents (__NR_Linux + 202)
++#define __NR_io_submit (__NR_Linux + 203)
++#define __NR_io_cancel (__NR_Linux + 204)
++#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
++
++#define io_syscall1(type,fname,sname,atype,a) \
++type fname(atype a) \
++{ \
++ register unsigned long __a0 asm("$4") = (unsigned long) a; \
++ register unsigned long __a3 asm("$7"); \
++ unsigned long __v0; \
++ \
++ __asm__ volatile ( \
++ ".set\tnoreorder\n\t" \
++ "li\t$2, %3\t\t\t# " #fname "\n\t" \
++ "syscall\n\t" \
++ "move\t%0, $2\n\t" \
++ ".set\treorder" \
++ : "=&r" (__v0), "=r" (__a3) \
++ : "r" (__a0), "i" (__NR_##sname) \
++ : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
++ "memory"); \
++ \
++ if (__a3 == 0) \
++ return (type) __v0; \
++ return (type) -1; \
++}
++
++#define io_syscall2(type,fname,sname,atype,a,btype,b) \
++type fname(atype a, btype b) \
++{ \
++ register unsigned long __a0 asm("$4") = (unsigned long) a; \
++ register unsigned long __a1 asm("$5") = (unsigned long) b; \
++ register unsigned long __a3 asm("$7"); \
++ unsigned long __v0; \
++ \
++ __asm__ volatile ( \
++ ".set\tnoreorder\n\t" \
++ "li\t$2, %4\t\t\t# " #fname "\n\t" \
++ "syscall\n\t" \
++ "move\t%0, $2\n\t" \
++ ".set\treorder" \
++ : "=&r" (__v0), "=r" (__a3) \
++ : "r" (__a0), "r" (__a1), "i" (__NR_##sname) \
++ : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
++ "memory"); \
++ \
++ if (__a3 == 0) \
++ return (type) __v0; \
++ return (type) -1; \
++}
++
++#define io_syscall3(type,fname,sname,atype,a,btype,b,ctype,c) \
++type fname(atype a, btype b, ctype c) \
++{ \
++ register unsigned long __a0 asm("$4") = (unsigned long) a; \
++ register unsigned long __a1 asm("$5") = (unsigned long) b; \
++ register unsigned long __a2 asm("$6") = (unsigned long) c; \
++ register unsigned long __a3 asm("$7"); \
++ unsigned long __v0; \
++ \
++ __asm__ volatile ( \
++ ".set\tnoreorder\n\t" \
++ "li\t$2, %5\t\t\t# " #fname "\n\t" \
++ "syscall\n\t" \
++ "move\t%0, $2\n\t" \
++ ".set\treorder" \
++ : "=&r" (__v0), "=r" (__a3) \
++ : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##sname) \
++ : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
++ "memory"); \
++ \
++ if (__a3 == 0) \
++ return (type) __v0; \
++ return (type) -1; \
++}
++
++#define io_syscall4(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d) \
++type fname(atype a, btype b, ctype c, dtype d) \
++{ \
++ register unsigned long __a0 asm("$4") = (unsigned long) a; \
++ register unsigned long __a1 asm("$5") = (unsigned long) b; \
++ register unsigned long __a2 asm("$6") = (unsigned long) c; \
++ register unsigned long __a3 asm("$7") = (unsigned long) d; \
++ unsigned long __v0; \
++ \
++ __asm__ volatile ( \
++ ".set\tnoreorder\n\t" \
++ "li\t$2, %5\t\t\t# " #fname "\n\t" \
++ "syscall\n\t" \
++ "move\t%0, $2\n\t" \
++ ".set\treorder" \
++ : "=&r" (__v0), "+r" (__a3) \
++ : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##sname) \
++ : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
++ "memory"); \
++ \
++ if (__a3 == 0) \
++ return (type) __v0; \
++ return (type) -1; \
++}
++
++#if (_MIPS_SIM == _MIPS_SIM_ABI32)
++
++/*
++ * Using those means your brain needs more than an oil change ;-)
++ */
++
++#define io_syscall5(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
++type fname(atype a, btype b, ctype c, dtype d, etype e) \
++{ \
++ register unsigned long __a0 asm("$4") = (unsigned long) a; \
++ register unsigned long __a1 asm("$5") = (unsigned long) b; \
++ register unsigned long __a2 asm("$6") = (unsigned long) c; \
++ register unsigned long __a3 asm("$7") = (unsigned long) d; \
++ unsigned long __v0; \
++ \
++ __asm__ volatile ( \
++ ".set\tnoreorder\n\t" \
++ "lw\t$2, %6\n\t" \
++ "subu\t$29, 32\n\t" \
++ "sw\t$2, 16($29)\n\t" \
++ "li\t$2, %5\t\t\t# " #fname "\n\t" \
++ "syscall\n\t" \
++ "move\t%0, $2\n\t" \
++ "addiu\t$29, 32\n\t" \
++ ".set\treorder" \
++ : "=&r" (__v0), "+r" (__a3) \
++ : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##sname), \
++ "m" ((unsigned long)e) \
++ : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
++ "memory"); \
++ \
++ if (__a3 == 0) \
++ return (type) __v0; \
++ return (type) -1; \
++}
++
++#endif /* (_MIPS_SIM == _MIPS_SIM_ABI32) */
++
++#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
++
++#define io_syscall5(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
++type fname (atype a,btype b,ctype c,dtype d,etype e) \
++{ \
++ register unsigned long __a0 asm("$4") = (unsigned long) a; \
++ register unsigned long __a1 asm("$5") = (unsigned long) b; \
++ register unsigned long __a2 asm("$6") = (unsigned long) c; \
++ register unsigned long __a3 asm("$7") = (unsigned long) d; \
++ register unsigned long __a4 asm("$8") = (unsigned long) e; \
++ unsigned long __v0; \
++ \
++ __asm__ volatile ( \
++ ".set\tnoreorder\n\t" \
++ "li\t$2, %6\t\t\t# " #fname "\n\t" \
++ "syscall\n\t" \
++ "move\t%0, $2\n\t" \
++ ".set\treorder" \
++ : "=&r" (__v0), "+r" (__a3) \
++ : "r" (__a0), "r" (__a1), "r" (__a2), "r" (__a4), "i" (__NR_##sname) \
++ : "$2", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
++ "memory"); \
++ \
++ if (__a3 == 0) \
++ return (type) __v0; \
++ return (type) -1; \
++}
++
++#endif /* (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) */
++
+--- libaio-0.3.106.orig/src/libaio.h
++++ libaio-0.3.106/src/libaio.h
+@@ -72,6 +72,40 @@
+ #define PADDED(x, y) unsigned y; x
+ #define PADDEDptr(x, y) unsigned y; x
+ #define PADDEDul(x, y) unsigned y; unsigned long x
++#elif defined(__arm__)
++# if defined (__ARMEB__) /* big endian, 32 bits */
++#define PADDED(x, y) unsigned y; x
++#define PADDEDptr(x, y) unsigned y; x
++#define PADDEDul(x, y) unsigned y; unsigned long x
++# else /* little endian, 32 bits */
++#define PADDED(x, y) x; unsigned y
++#define PADDEDptr(x, y) x; unsigned y
++#define PADDEDul(x, y) unsigned long x; unsigned y
++# endif
++#elif defined(__m68k__) /* big endian, 32 bits */
++#define PADDED(x, y) unsigned y; x
++#define PADDEDptr(x, y) unsigne%s
>>> DIFF TRUNCATED @ 16K
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