[oe-commits] org.oe.dev logicpd-pxa270 2.6.19.2: update kernel, contributed by Shane Volpe
cbrake commit
openembedded-commits at lists.openembedded.org
Wed Jan 31 13:39:48 UTC 2007
logicpd-pxa270 2.6.19.2: update kernel, contributed by Shane Volpe
Author: cbrake at openembedded.org
Branch: org.openembedded.dev
Revision: 8e1fbabc03aa096ccfb8a78008be524548d03983
ViewMTN: http://monotone.openembedded.org/revision.psp?id=8e1fbabc03aa096ccfb8a78008be524548d03983
Files:
1
packages/linux/logicpd-pxa270-2.6.19.2
packages/linux/logicpd-pxa270-2.6.19.2/asoc-v0.12.4.patch
packages/linux/logicpd-pxa270-2.6.19.2/config-nr-tty-devices.patch
packages/linux/logicpd-pxa270-2.6.19.2/defconfig-logicpd-pxa270
packages/linux/logicpd-pxa270-2.6.19.2/input_power-r6.patch
packages/linux/logicpd-pxa270-2.6.19.2/kexec-arm-r3.patch
packages/linux/logicpd-pxa270-2.6.19.2/logicpd-pxa270-cf-hack.patch
packages/linux/logicpd-pxa270-2.6.19.2/logicpd-pxa270-flash.patch
packages/linux/logicpd-pxa270-2.6.19.2/logicpd-pxa270-hardware-id-hack.patch
packages/linux/logicpd-pxa270-2.6.19.2/logicpd-pxa270-lcd-osd024ttea2.patch
packages/linux/logicpd-pxa270-2.6.19.2/logicpd-pxa270-smc91x.patch
packages/linux/logicpd-pxa270-2.6.19.2/pm_changes-r1.patch
packages/linux/logicpd-pxa270-2.6.19.2/pxa25x_cpufreq-r1.patch
packages/linux/logicpd-pxa270-2.6.19.2/pxa27x_overlay-r4.patch
packages/linux/logicpd-pxa270-2.6.19.2/pxa_irda_susres_fix-r0.patch
packages/linux/logicpd-pxa270-2.6.19.2/pxa_keys-r5.patch
packages/linux/logicpd-pxa270-2.6.19.2/pxa_timerfix-r0.patch
packages/linux/logicpd-pxa270-2.6.19.2/pxafb_fix_params-r2.patch
packages/linux/logicpd-pxa270-2.6.19.2/ucb1400-touchscreen.patch
packages/linux/logicpd-pxa270-2.6.19.2/usb_add_epalloc-r3.patch
packages/linux/logicpd-pxa270-2.6.19.2/usb_pxa27x_udc-r3.patch
packages/linux/logicpd-pxa270-2.6.19.2/xscale_cache_workaround-r1.patch
packages/linux/logicpd-pxa270_2.6.19.2.bb
conf/machine/logicpd-pxa270.conf
Diffs:
#
# mt diff -r8744af1b6b5973503029b09054861a7f77dad32d -r8e1fbabc03aa096ccfb8a78008be524548d03983
#
#
#
# add_dir "packages/linux/logicpd-pxa270-2.6.19.2"
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/asoc-v0.12.4.patch"
# content [a43a23f919c28750a896f965f9370c29f29e1519]
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/config-nr-tty-devices.patch"
# content [789ea4fcc84319bcbaec2649573b856fa50193da]
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/defconfig-logicpd-pxa270"
# content [379ec753762bb5e3ac8b68a5e16ffc250cfaa537]
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/input_power-r6.patch"
# content [80f342214b47b991617ad5eaa037f5295bff9a0b]
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/kexec-arm-r3.patch"
# content [86cb152391b7ad4adcf6da95d971c7cc159bb4f9]
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/logicpd-pxa270-cf-hack.patch"
# content [db7ad2a8ce242d2e0395769294a8361d1d5b42e9]
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/logicpd-pxa270-flash.patch"
# content [a555c5b29653d8eae9daed7af7a324057fbb459d]
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/logicpd-pxa270-hardware-id-hack.patch"
# content [e1683604ec32c522cc75602d36f847aa988529c1]
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/logicpd-pxa270-lcd-osd024ttea2.patch"
# content [3785408675c09514b23039e5fbd026ee1ef1d87e]
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/logicpd-pxa270-smc91x.patch"
# content [d3039b2150cce395a29874cf886d325272dea619]
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/pm_changes-r1.patch"
# content [72ea135a695fb0ff8b9a2eb4c4ebc0973f1eaf90]
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/pxa25x_cpufreq-r1.patch"
# content [042dbd001507bb25b6814b78c3b7efa3111f5bb7]
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/pxa27x_overlay-r4.patch"
# content [c297471b732d21ffcc26bbb49fef0b8623654a3a]
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/pxa_irda_susres_fix-r0.patch"
# content [3f641a130e8039dd0f9edb8dff2ac51bed1249f2]
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/pxa_keys-r5.patch"
# content [2bb43fcdf22c5cfd481b29c4e5f3755fd2ff7d78]
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/pxa_timerfix-r0.patch"
# content [e3fdcbedf8e53ff35e9eda417d53a5b8da3f6f5c]
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/pxafb_fix_params-r2.patch"
# content [3adadb3ad92b5fbeaa6836ffcabb884963a1ea23]
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/ucb1400-touchscreen.patch"
# content [5996e6546434f9e4582985ebc0a13a9f9b8d6b72]
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/usb_add_epalloc-r3.patch"
# content [de4731c911c7bc117a4f44859107e9cb69085b1b]
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/usb_pxa27x_udc-r3.patch"
# content [9db608e70b4d7bfa4483c2fee98d9c23f2d7f6a8]
#
# add_file "packages/linux/logicpd-pxa270-2.6.19.2/xscale_cache_workaround-r1.patch"
# content [86b290f1e4d0dd8ef351a36e8897a3d07c60b832]
#
# add_file "packages/linux/logicpd-pxa270_2.6.19.2.bb"
# content [f4207e81635c59f6a4f04f0ea09683fef6ed465d]
#
# patch "conf/machine/logicpd-pxa270.conf"
# from [d66de7eee7676ab02110a2613df696d49ab27557]
# to [4de435919f3ea2cd84e1509394d9a652021de9e4]
#
============================================================
--- packages/linux/logicpd-pxa270-2.6.19.2/asoc-v0.12.4.patch a43a23f919c28750a896f965f9370c29f29e1519
+++ packages/linux/logicpd-pxa270-2.6.19.2/asoc-v0.12.4.patch a43a23f919c28750a896f965f9370c29f29e1519
@@ -0,0 +1,31712 @@
+Index: linux-2.6-pxa-new/Documentation/sound/alsa/soc/DAI.txt
+===================================================================
+--- /dev/null
++++ linux-2.6-pxa-new/Documentation/sound/alsa/soc/DAI.txt
+@@ -0,0 +1,546 @@
++ASoC currently supports the three main Digital Audio Interfaces (DAI) found on
++SoC controllers and portable audio CODECS today, namely AC97, I2S and PCM.
++
++
++AC97
++====
++
++ AC97 is a five wire interface commonly found on many PC sound cards. It is
++now also popular in many portable devices. This DAI has a reset line and time
++multiplexes its data on its SDATA_OUT (playback) and SDATA_IN (capture) lines.
++The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the
++frame (FRAME) (usually 48kHz) is always driven by the controller. Each AC97
++frame is 21uS long and is divided into 13 time slots.
++
++The AC97 specification can be found at :-
++http://www.intel.com/design/chipsets/audio/ac97_r23.pdf
++
++
++I2S
++===
++
++ I2S is a common 4 wire DAI used in HiFi, STB and portable devices. The Tx and
++Rx lines are used for audio transmision, whilst the bit clock (BCLK) and
++left/right clock (LRC) synchronise the link. I2S is flexible in that either the
++controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
++usually varies depending on the sample rate and the master system clock
++(SYSCLK). LRCLK is the same as the sample rate. A few devices support separate
++ADC and DAC LRCLK's, this allows for similtanious capture and playback at
++different sample rates.
++
++I2S has several different operating modes:-
++
++ o I2S - MSB is transmitted on the falling edge of the first BCLK after LRC
++ transition.
++
++ o Left Justified - MSB is transmitted on transition of LRC.
++
++ o Right Justified - MSB is transmitted sample size BCLK's before LRC
++ transition.
++
++PCM
++===
++
++PCM is another 4 wire interface, very similar to I2S, that can support a more
++flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used
++to synchronise the link whilst the Tx and Rx lines are used to transmit and
++receive the audio data. Bit clock usually varies depending on sample rate
++whilst sync runs at the sample rate. PCM also supports Time Division
++Multiplexing (TDM) in that several devices can use the bus similtaniuosly (This
++is sometimes referred to as network mode).
++
++Common PCM operating modes:-
++
++ o Mode A - MSB is transmitted on falling edge of first BCLK after FRAME/SYNC.
++
++ o Mode B - MSB is transmitted on rising edge of FRAME/SYNC.
++
++
++ASoC DAI Configuration
++======================
++
++Every CODEC DAI and SoC DAI must have their capabilities defined in order to
++be configured together at runtime when the audio and clocking parameters are
++known. This is achieved by creating an array of struct snd_soc_hw_mode in the
++the CODEC and SoC interface drivers. Each element in the array describes a DAI
++mode and each mode is usually based upon the DAI system clock to sample rate
++ratio (FS).
++
++i.e. 48k sample rate @ 256 FS = sytem clock of 12.288 MHz
++ 48000 * 256 = 12288000
++
++The CPU and Codec DAI modes are then ANDed together at runtime to determine the
++rutime DAI configuration for both the Codec and CPU.
++
++When creating a new codec or SoC DAI it's probably best to start of with a few
++sample rates first and then test your interface.
++
++struct snd_soc_dai_mode is defined (in soc.h) as:-
++
++/* SoC DAI mode */
++struct snd_soc_dai_mode {
++ u16 fmt; /* SND_SOC_DAIFMT_* */
++ u16 tdm; /* SND_SOC_HWTDM_* */
++ u64 pcmfmt; /* SNDRV_PCM_FMTBIT_* */
++ u16 pcmrate; /* SND_SOC_HWRATE_* */
++ u16 pcmdir:2; /* SND_SOC_HWDIR_* */
++ u16 flags:8; /* hw flags */
++ u16 fs; /* mclk to rate divider */
++ u64 bfs; /* mclk to bclk dividers */
++ unsigned long priv; /* private mode data */
++};
++
++fmt:
++----
++This field defines the DAI mode hardware format (e.g. I2S settings) and
++supports the following settings:-
++
++ 1) hardware DAI formats
++
++#define SND_SOC_DAIFMT_I2S (1 << 0) /* I2S mode */
++#define SND_SOC_DAIFMT_RIGHT_J (1 << 1) /* Right justified mode */
++#define SND_SOC_DAIFMT_LEFT_J (1 << 2) /* Left Justified mode */
++#define SND_SOC_DAIFMT_DSP_A (1 << 3) /* L data msb after FRM */
++#define SND_SOC_DAIFMT_DSP_B (1 << 4) /* L data msb during FRM */
++#define SND_SOC_DAIFMT_AC97 (1 << 5) /* AC97 */
++
++ 2) hw DAI signal inversions
++
++#define SND_SOC_DAIFMT_NB_NF (1 << 8) /* normal bit clock + frame */
++#define SND_SOC_DAIFMT_NB_IF (1 << 9) /* normal bclk + inv frm */
++#define SND_SOC_DAIFMT_IB_NF (1 << 10) /* invert bclk + nor frm */
++#define SND_SOC_DAIFMT_IB_IF (1 << 11) /* invert bclk + frm */
++
++ 3) hw clock masters
++ This is wrt the codec, the inverse is true for the interface
++ i.e. if the codec is clk and frm master then the interface is
++ clk and frame slave.
++
++#define SND_SOC_DAIFMT_CBM_CFM (1 << 12) /* codec clk & frm master */
++#define SND_SOC_DAIFMT_CBS_CFM (1 << 13) /* codec clk slave & frm master */
++#define SND_SOC_DAIFMT_CBM_CFS (1 << 14) /* codec clk master & frame slave */
++#define SND_SOC_DAIFMT_CBS_CFS (1 << 15) /* codec clk & frm slave */
++
++At least one option from each section must be selected. Multiple selections are
++also supported e.g.
++
++ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_RIGHT_J | \
++ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_NB_IF | SND_SOC_DAIFMT_IB_NF | \
++ SND_SOC_DAIFMT_IB_IF
++
++
++tdm:
++------
++This field defines the Time Division Multiplexing left and right word
++positions for the DAI mode if applicable. Set to SND_SOC_DAITDM_LRDW(0,0) for
++no TDM.
++
++
++pcmfmt:
++---------
++The hardware PCM format. This describes the PCM formats supported by the DAI
++mode e.g.
++
++ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
++ SNDRV_PCM_FORMAT_S24_3LE
++
++pcmrate:
++----------
++The PCM sample rates supported by the DAI mode. e.g.
++
++ .pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
++ SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
++ SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000
++
++
++pcmdir:
++---------
++The stream directions supported by this mode. e.g. playback and capture
++
++
++flags:
++--------
++The DAI hardware flags supported by the mode.
++
++/* use bfs mclk divider mode (BCLK = MCLK / x) */
++#define SND_SOC_DAI_BFS_DIV 0x1
++/* use bfs rate mulitplier (BCLK = RATE * x)*/
++#define SND_SOC_DAI_BFS_RATE 0x2
++/* use bfs rcw multiplier (BCLK = RATE * CHN * WORD SIZE) */
++#define SND_SOC_DAI_BFS_RCW 0x4
++/* capture and playback can use different clocks */
++#define SND_SOC_DAI_ASYNC 0x8
++
++NOTE: Bitclock division and mulitiplication modes can be safely matched by the
++core logic.
++
++
++fs:
++-----
++The FS supported by this DAI mode FS is the ratio between the system clock and
++the sample rate. See above
++
++bfs:
++------
++BFS is the ratio of BCLK to MCLK or the ratio of BCLK to sample rate (this
++depends on the codec or CPU DAI).
++
++The BFS supported by the DAI mode. This can either be the ratio between the
++bitclock (BCLK) and the sample rate OR the ratio between the system clock and
++the sample rate. Depends on the flags above.
++
++priv:
++-----
++private codec mode data.
++
++
++
++Examples
++========
++
++Note that Codec DAI and CPU DAI examples are interchangeable in these examples
++as long as the bus master is reversed. i.e.
++
++ SND_SOC_DAIFMT_CBM_CFM would become SND_SOC_DAIFMT_CBS_CFS
++ and vice versa.
++
++This applies to all SND_SOC_DAIFMT_CB*_CF*.
++
++Example 1
++---------
++
++Simple codec that only runs at 8k & 48k @ 256FS in master mode, can generate a
++BCLK of either MCLK/2 or MCLK/4.
++
++ /* codec master */
++ {
++ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
++ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
++ .pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
++ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
++ .flags = SND_SOC_DAI_BFS_DIV,
++ .fs = 256,
++ .bfs = SND_SOC_FSBD(2) | SND_SOC_FSBD(4),
++ }
++
++
++Example 2
++---------
++Simple codec that only runs at 8k & 48k @ 256FS in master mode, can generate a
++BCLK of either Rate * 32 or Rate * 64.
++
++ /* codec master */
++ {
++ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
++ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
++ .pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
++ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
++ .flags = SND_SOC_DAI_BFS_RATE,
++ .fs = 256,
++ .bfs = 32,
++ },
++ {
++ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
++ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
++ .pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
++ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
++ .flags = SND_SOC_DAI_BFS_RATE,
++ .fs = 256,
++ .bfs = 64,
++ },
++
++
++Example 3
++---------
++Codec that runs at 8k & 48k @ 256FS in master mode, can generate a BCLK that
++is a multiple of Rate * channels * word size. (RCW) i.e.
++
++ BCLK = 8000 * 2 * 16 (8k, stereo, 16bit)
++ = 256kHz
++
++This codecs supports a RCW multiple of 1,2
++
++ {
++ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
++ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
++ .pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
++ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
++ .flags = SND_SOC_DAI_BFS_RCW,
++ .fs = 256,
++ .bfs = SND_SOC_FSBW(1) | SND_SOC_FSBW(2),
++ }
++
++
++Example 4
++---------
++Codec that only runs at 8k & 48k @ 256FS in master mode, can generate a
++BCLK of either Rate * 32 or Rate * 64. Codec can also run in slave mode as long
++as BCLK is rate * 32 or rate * 64.
++
++ /* codec master */
++ {
++ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
++ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
++ .pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
++ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
++ .flags = SND_SOC_DAI_BFS_RATE,
++ .fs = 256,
++ .bfs = 32,
++ },
++ {
++ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
++ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
++ .pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
++ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
++ .flags = SND_SOC_DAI_BFS_RATE,
++ .fs = 256,
++ .bfs = 64,
++ },
++
++ /* codec slave */
++ {
++ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS,
++ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
++ .pcmdir = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
++ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
++ .flags = SND_SOC_DAI_BFS_RATE,
++ .fs = SND_SOC_FS_ALL,
++ .bfs = 32,
++ },
++ {
++ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS,
++ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
++ .pcmdir = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
++ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
++ .flags = SND_SOC_DAI_BFS_RATE,
++ .fs = SND_SOC_FS_ALL,
++ .bfs = 64,
++ },
++
++
++Example 5
++---------
++Codec that only runs at 8k, 16k, 32k, 48k, 96k @ 128FS, 192FS & 256FS in master
++mode and can generate a BCLK of MCLK / (1,2,4,8,16). Codec can also run in slave
++mode as and does not care about FS or BCLK (as long as there is enough bandwidth).
++
++ #define CODEC_FSB \
++ (SND_SOC_FSBD(1) | SND_SOC_FSBD(2) | SND_SOC_FSBD(4) | \
++ SND_SOC_FSBD(8) | SND_SOC_FSBD(16))
++
++ #define CODEC_RATES \
++ (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 |\
++ SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
++
++ /* codec master @ 128, 192 & 256 FS */
++ {
++ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
++ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
++ .pcmrate = CODEC_RATES,
++ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
++ .flags = SND_SOC_DAI_BFS_DIV,
++ .fs = 128,
++ .bfs = CODEC_FSB,
++ },
++
++ {
++ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
++ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
++ .pcmrate = CODEC_RATES,
++ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
++ .flags = SND_SOC_DAI_BFS_DIV,
++ .fs = 192,
++ .bfs = CODEC_FSB
++ },
++
++ {
++ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
++ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
++ .pcmrate = CODEC_RATES,
++ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
++ .flags = SND_SOC_DAI_BFS_DIV,
++ .fs = 256,
++ .bfs = CODEC_FSB,
++ },
++
++ /* codec slave */
++ {
++ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS,
++ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
++ .pcmrate = CODEC_RATES,
++ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
++ .fs = SND_SOC_FS_ALL,
++ .bfs = SND_SOC_FSB_ALL,
++ },
++
++
++Example 6
++---------
++Codec that only runs at 8k, 44.1k, 48k @ different FS in master mode (for use
++with a fixed MCLK) and can generate a BCLK of MCLK / (1,2,4,8,16).
++Codec ca%s
>>> DIFF TRUNCATED @ 16K
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