[oe-commits] org.oe.dev u-boot_1.3.2.bb: add patches for mpc8313e-rdb
jeremy_laine commit
oe at amethyst.openembedded.net
Wed Apr 30 12:30:54 UTC 2008
u-boot_1.3.2.bb: add patches for mpc8313e-rdb
Author: jeremy_laine at openembedded.org
Branch: org.openembedded.dev
Revision: 5b1c73beb325cedc73f912683595bfe31eac6f31
ViewMTN: http://monotone.openembedded.org/revision/info/5b1c73beb325cedc73f912683595bfe31eac6f31
Files:
1
packages/u-boot/u-boot-1.3.2
packages/u-boot/u-boot-1.3.2/mpc8313e-rdb-autoboot.patch
packages/u-boot/u-boot-1.3.2/mpc8313e-rdb-mtdparts.patch
packages/u-boot/u-boot-1.3.2/mpc8313e-rdb-nand.patch
packages/u-boot/u-boot_1.3.2.bb
Diffs:
#
# mt diff -r26a2db272eb8a8c45759850000cba2e07e5de47e -r5b1c73beb325cedc73f912683595bfe31eac6f31
#
#
#
# add_dir "packages/u-boot/u-boot-1.3.2"
#
# add_file "packages/u-boot/u-boot-1.3.2/mpc8313e-rdb-autoboot.patch"
# content [d10d1edb2510c27cbbfca47e962cfc8da45f0788]
#
# add_file "packages/u-boot/u-boot-1.3.2/mpc8313e-rdb-mtdparts.patch"
# content [20746984bb1c6ef2789381da1283a8e06a74b0ac]
#
# add_file "packages/u-boot/u-boot-1.3.2/mpc8313e-rdb-nand.patch"
# content [64eee6cc9ba75710f130f074b0632df44049ca14]
#
# patch "packages/u-boot/u-boot_1.3.2.bb"
# from [8cfd5293c0214179a38b2304fbd10c77a3912aff]
# to [33ac513192e4695c4ea43a787d866c98c2a011ef]
#
============================================================
--- packages/u-boot/u-boot-1.3.2/mpc8313e-rdb-autoboot.patch d10d1edb2510c27cbbfca47e962cfc8da45f0788
+++ packages/u-boot/u-boot-1.3.2/mpc8313e-rdb-autoboot.patch d10d1edb2510c27cbbfca47e962cfc8da45f0788
@@ -0,0 +1,12 @@
+diff -urN u-boot-1.3.1.orig/include/configs/MPC8313ERDB.h u-boot-1.3.1/include/configs/MPC8313ERDB.h
+--- u-boot-1.3.1.orig/include/configs/MPC8313ERDB.h 2007-12-06 10:21:19.000000000 +0100
++++ u-boot-1.3.1/include/configs/MPC8313ERDB.h 2008-01-31 17:38:10.000000000 +0100
+@@ -522,7 +522,7 @@
+ #define CONFIG_FDTFILE mpc8313erdb.dtb
+
+ #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
+-#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
++#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
+ #define CONFIG_BAUDRATE 115200
+
+ #define XMK_STR(x) #x
============================================================
--- packages/u-boot/u-boot-1.3.2/mpc8313e-rdb-mtdparts.patch 20746984bb1c6ef2789381da1283a8e06a74b0ac
+++ packages/u-boot/u-boot-1.3.2/mpc8313e-rdb-mtdparts.patch 20746984bb1c6ef2789381da1283a8e06a74b0ac
@@ -0,0 +1,35 @@
+diff -urN u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h u-boot-1.3.2/include/configs/MPC8313ERDB.h
+--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h 2008-03-09 16:20:02.000000000 +0100
++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h 2008-04-21 19:20:51.000000000 +0200
+@@ -179,7 +179,7 @@
+ #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+ /* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
+-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
++#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
+ #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+
+ /*
+@@ -354,6 +354,7 @@
+ #define CONFIG_CMD_PING
+ #define CONFIG_CMD_DHCP
+ #define CONFIG_CMD_I2C
++#define CONFIG_CMD_JFFS2
+ #define CONFIG_CMD_MII
+ #define CONFIG_CMD_DATE
+ #define CONFIG_CMD_PCI
+@@ -365,6 +366,14 @@
+
+ #define CONFIG_CMDLINE_EDITING 1
+
++/*
++ * JFFS2 partitions (mtdparts command line support)
++ */
++#define CONFIG_JFFS2_CMDLINE
++#define CONFIG_JFFS2_NAND
++#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand0"
++#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:384k(uboot),64k(env)"
++
+
+ /*
+ * Miscellaneous configurable options
============================================================
--- packages/u-boot/u-boot-1.3.2/mpc8313e-rdb-nand.patch 64eee6cc9ba75710f130f074b0632df44049ca14
+++ packages/u-boot/u-boot-1.3.2/mpc8313e-rdb-nand.patch 64eee6cc9ba75710f130f074b0632df44049ca14
@@ -0,0 +1,895 @@
+diff -urN u-boot-1.3.1.orig/board/freescale/mpc8313erdb/Makefile u-boot-1.3.1/board/freescale/mpc8313erdb/Makefile
+--- u-boot-1.3.1.orig/board/freescale/mpc8313erdb/Makefile 2007-12-06 10:21:19.000000000 +0100
++++ u-boot-1.3.1/board/freescale/mpc8313erdb/Makefile 2008-01-31 17:35:43.000000000 +0100
+@@ -25,7 +25,7 @@
+
+ LIB = $(obj)lib$(BOARD).a
+
+-COBJS := $(BOARD).o sdram.o
++COBJS := $(BOARD).o sdram.o nand.o
+
+ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+ OBJS := $(addprefix $(obj),$(COBJS))
+diff -urN u-boot-1.3.1.orig/board/freescale/mpc8313erdb/nand.c u-boot-1.3.1/board/freescale/mpc8313erdb/nand.c
+--- u-boot-1.3.1.orig/board/freescale/mpc8313erdb/nand.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.3.1/board/freescale/mpc8313erdb/nand.c 2008-01-31 17:35:26.000000000 +0100
+@@ -0,0 +1,868 @@
++/*
++ * Copyright (C) Freescale Semiconductor, Inc. 2006.
++ *
++ * Initialized by Nick.Spence at freescale.com
++ * Wilson.Lo at freescale.com
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++
++#if defined(CONFIG_CMD_NAND)
++#if defined(CFG_NAND_LEGACY)
++ #error "U-Boot legacy NAND commands not supported."
++#else
++
++#include <malloc.h>
++#include <asm/errno.h>
++#include <nand.h>
++
++#undef CFG_FCM_DEBUG
++#define CFG_FCM_DEBUG_LVL 1
++#ifdef CFG_FCM_DEBUG
++#define FCM_DEBUG(n, args...) \
++ do { \
++ if (n <= (CFG_FCM_DEBUG_LVL + 0)) \
++ printf(args); \
++ } while(0)
++#else /* CONFIG_FCM_DEBUG */
++#define FCM_DEBUG(n, args...) do { } while(0)
++#endif
++
++#define MIN(x, y) ((x < y) ? x : y)
++
++#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
++
++#define FCM_TIMEOUT_USECS 100000 /* Maximum number of uSecs to wait for FCM */
++
++/* Private structure holding NAND Flash device specific information */
++struct fcm_nand {
++ int bank; /* Chip select bank number */
++ unsigned int base; /* Chip select base address */
++ int pgs; /* NAND page size */
++ int oobbuf; /* Pointer to OOB block */
++ unsigned int page; /* Last page written to / read from */
++ unsigned int fmr; /* FCM Flash Mode Register value */
++ unsigned int mdr; /* UPM/FCM Data Register value */
++ unsigned int use_mdr; /* Non zero if the MDR is to be set */
++ u_char *addr; /* Address of assigned FCM buffer */
++ unsigned int read_bytes; /* Number of bytes read during command */
++ unsigned int index; /* Pointer to next byte to 'read' */
++ unsigned int req_bytes; /* Number of bytes read if command ok */
++ unsigned int req_index; /* New read index if command ok */
++ unsigned int status; /* status read from LTESR after last op*/
++};
++
++
++/* These map to the positions used by the FCM hardware ECC generator */
++
++/* Small Page FLASH with FMR[ECCM] = 0 */
++static struct nand_oobinfo fcm_oob_sp_eccm0 = { /* TODO */
++ .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */
++ .eccbytes = 3,
++ .eccpos = {6, 7, 8},
++ .oobfree = { {0, 5}, {9, 7} }
++};
++
++/* Small Page FLASH with FMR[ECCM] = 1 */
++static struct nand_oobinfo fcm_oob_sp_eccm1 = { /* TODO */
++ .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */
++ .eccbytes = 3,
++ .eccpos = {8, 9, 10},
++ .oobfree = { {0, 5}, {6, 2}, {11, 5} }
++};
++
++/* Large Page FLASH with FMR[ECCM] = 0 */
++static struct nand_oobinfo fcm_oob_lp_eccm0 = {
++ .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */
++ .eccbytes = 12,
++ .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
++ .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} }
++};
++
++/* Large Page FLASH with FMR[ECCM] = 1 */
++static struct nand_oobinfo fcm_oob_lp_eccm1 = {
++ .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */
++ .eccbytes = 12,
++ .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
++ .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} }
++};
++
++/*
++ * execute FCM command and wait for it to complete
++ */
++static int fcm_run_command(struct mtd_info *mtd)
++{
++ volatile immap_t *im = (immap_t *) CFG_IMMR;
++ volatile lbus83xx_t *lbc= &im->lbus;
++ register struct nand_chip *this = mtd->priv;
++ struct fcm_nand *fcm = this->priv;
++ long long end_tick;
++
++ /* Setup the FMR[OP] to execute without write protection */
++ lbc->fmr = fcm->fmr | 3;
++ if (fcm->use_mdr)
++ lbc->mdr = fcm->mdr;
++
++ FCM_DEBUG(5,"fcm_run_command: fmr= %08X fir= %08X fcr= %08X\n",
++ lbc->fmr, lbc->fir, lbc->fcr);
++ FCM_DEBUG(5,"fcm_run_command: fbar=%08X fpar=%08X fbcr=%08X bank=%d\n",
++ lbc->fbar, lbc->fpar, lbc->fbcr, fcm->bank);
++
++ /* clear event registers */
++ lbc->lteatr = 0;
++ lbc->ltesr |= (LTESR_FCT | LTESR_PAR | LTESR_CC);
++
++ /* execute special operation */
++ lbc->lsor = fcm->bank;
++
++ /* wait for FCM complete flag or timeout */
++ fcm->status = 0;
++ end_tick = usec2ticks(FCM_TIMEOUT_USECS) + get_ticks();
++
++ while (end_tick > get_ticks()) {
++ if (lbc->ltesr & LTESR_CC) {
++ fcm->status = lbc->ltesr &
++ (LTESR_FCT | LTESR_PAR | LTESR_CC);
++ break;
++ }
++ }
++
++ /* store mdr value in case it was needed */
++ if (fcm->use_mdr)
++ fcm->mdr = lbc->mdr;
++
++ fcm->use_mdr = 0;
++
++ FCM_DEBUG(5,"fcm_run_command: stat=%08X mdr= %08X fmr= %08X\n",
++ fcm->status, fcm->mdr, lbc->fmr);
++
++ /* if the operation completed ok then set the read buffer pointers */
++ if (fcm->status == LTESR_CC) {
++ fcm->read_bytes = fcm->req_bytes;
++ fcm->index = fcm->req_index;
++ return 0;
++ }
++
++ return -1;
++}
++
++/*
++ * Set up the FCM hardware block and page address fields, and the fcm
++ * structure addr field to point to the correct FCM buffer in memory
++ */
++static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
++{
++ volatile immap_t *im = (immap_t *) CFG_IMMR;
++ volatile lbus83xx_t *lbc= &im->lbus;
++ register struct nand_chip *this = mtd->priv;
++ struct fcm_nand *fcm = this->priv;
++ int buf_num;
++
++ fcm->page = page_addr;
++
++ lbc->fbar = page_addr >> (this->phys_erase_shift - this->page_shift);
++ if (fcm->pgs) {
++ lbc->fpar = ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
++ ( oob ? FPAR_LP_MS : 0) |
++ column;
++ buf_num = (page_addr & 1) << 2;
++ } else {
++ lbc->fpar = ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
++ ( oob ? FPAR_SP_MS : 0) |
++ column;
++ buf_num = page_addr & 7;
++ }
++ fcm->addr = (unsigned char*)(fcm->base + (buf_num * 1024));
++
++ /* for OOB data point to the second half of the buffer */
++ if (oob) {
++ fcm->addr += (fcm->pgs ? 2048 : 512);
++ }
++}
++
++/* not required for FCM */
++static void fcm_hwcontrol(struct mtd_info *mtdinfo, int cmd)
++{
++ return;
++}
++
++
++/*
++ * FCM does not support 16 bit data busses
++ */
++static u16 fcm_read_word(struct mtd_info *mtd)
++{
++ printf("fcm_read_word: UNIMPLEMENTED.\n");
++ return 0;
++}
++static void fcm_write_word(struct mtd_info *mtd, u16 word)
++{
++ printf("fcm_write_word: UNIMPLEMENTED.\n");
++}
++
++/*
++ * Write buf to the FCM Controller Data Buffer
++ */
++static void fcm_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
++{
++ register struct nand_chip *this = mtd->priv;
++ struct fcm_nand *fcm = this->priv;
++
++ FCM_DEBUG(3,"fcm_write_buf: writing %d bytes starting with 0x%x"
++ " at %d.\n", len, *((unsigned long*) buf), fcm->index);
++
++ /* If armed catch the address of the OOB buffer so that it can be */
++ /* updated with the real signature after the program comletes */
++ if (!fcm->oobbuf)
++ fcm->oobbuf = (int) buf;
++
++ /* copy the data into the FCM hardware buffer and update the index */
++ memcpy(&(fcm->addr[fcm->index]), buf, len);
++ fcm->index += len;
++ return;
++}
++
++
++/*
++ * FCM does not support individual writes. Instead these are either commands
++ * or data being written, both of which are handled through the cmdfunc
++ * handler.
++ */
++static void fcm_write_byte(struct mtd_info *mtd, u_char byte)
++{
++ printf("fcm_write_byte: UNIMPLEMENTED.\n");
++}
++
++/*
++ * read a byte from either the FCM hardware buffer if it has any data left
++ * otherwise issue a command to read a single byte.
++ */
++static u_char fcm_read_byte(struct mtd_info *mtd)
++{
++ volatile immap_t *im = (immap_t *) CFG_IMMR;
++ volatile lbus83xx_t *lbc= &im->lbus;
++ register struct nand_chip *this = mtd->priv;
++ struct fcm_nand *fcm = this->priv;
++ unsigned char byte;
++
++ /* If there are still bytes in the FCM then use the next byte */
++ if(fcm->index < fcm->read_bytes) {
++ byte = fcm->addr[(fcm->index)++];
++ FCM_DEBUG(4,"fcm_read_byte: byte %u (%02X): %d of %d.\n",
++ byte, byte, fcm->index-1, fcm->read_bytes);
++ } else {
++ /* otherwise issue a command to read 1 byte */
++ lbc->fir = (FIR_OP_RSW << FIR_OP0_SHIFT);
++ fcm->use_mdr = 1;
++ fcm->read_bytes = 0;
++ fcm->index = 0;
++ fcm->req_bytes = 0;
++ fcm->req_index = 0;
++ byte = fcm_run_command(mtd) ? ERR_BYTE : fcm->mdr & 0xff;
++ FCM_DEBUG(4,"fcm_read_byte: byte %u (%02X) from bus.\n",
++ byte, byte);
++ }
++
++ return byte;
++}
++
++
++/*
++ * Read from the FCM Controller Data Buffer
++ */
++static void fcm_read_buf(struct mtd_info *mtd, u_char* buf, int len)
++{
++ volatile immap_t *im = (immap_t *) CFG_IMMR;
++ volatile lbus83xx_t *lbc= &im->lbus;
++ register struct nand_chip *this = mtd->priv;
++ struct fcm_nand *fcm = this->priv;
++ int i;
++ int rest;
++
++ FCM_DEBUG(3,"fcm_read_buf: reading %d bytes.\n", len);
++
++ /* If last read failed then return error bytes */
++ if (fcm->status != LTESR_CC) {
++ /* just keep copying bytes so that the oob works */
++ memcpy(buf, &(fcm->addr[(fcm->index)]), len);
++ fcm->index += len;
++ }
++ else
++ {
++ /* see how much is still in the FCM buffer */
++ i = min(len, (fcm->read_bytes - fcm->index));
++ rest = i - len;
++ len = i;
++
++ memcpy(buf, &(fcm->addr[(fcm->index)]), len);
++ fcm->index += len;
++
++ /* If more data is needed then issue another block read */
++ if (rest) {
++ FCM_DEBUG(3,"fcm_read_buf: getting %d more bytes.\n",
++ rest);
++ buf += len;
++ lbc->fir = (FIR_OP_RBW << FIR_OP0_SHIFT);
++ set_addr(mtd, 0, 0, 0);
++ lbc->fbcr = rest;
++ fcm->req_bytes = lbc->fbcr;
++ fcm->req_index = 0;
++ fcm->use_mdr = 0;
++ if (!fcm_run_command(mtd))
++ fcm_read_buf(mtd, buf, rest);
++ else
++ memcpy(buf, fcm->addr, rest);
++ }
++ }
++ return;
++}
++
++
++/*
++ * Verify buffer against the FCM Controller Data Buffer
++ */
++static int fcm_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
++{
++ volatile immap_t *im = (immap_t *) CFG_IMMR;
++ volatile lbus83xx_t *lbc= &im->lbus;
++ register struct nand_chip *this = mtd->priv;
++ struct fcm_nand *fcm = this->priv;
++ int i;
++ int rest;
++
++ FCM_DEBUG(3,"fcm_verify_buf: checking %d bytes starting with 0x%02x.\n",
++ len, *((unsigned long*) buf));
++ /* If last read failed then return error bytes */
++ if (fcm->status != LTESR_CC) {
++ return EFAULT;
++ }
++
++ /* see how much is still in the FCM buffer */
++ i = min(len, (fcm->read_bytes - fcm->index));
++ rest = i - len;
++ len = i;
++
++ if (memcmp(buf, &(fcm->addr[(fcm->index)]), len)) {
++ return EFAULT;
++ }
++
++ fcm->index += len;
++ if (rest) {
++ FCM_DEBUG(3,"fcm_verify_buf: getting %d more bytes.\n", rest);
++ buf += len;
++ lbc->fir = (FIR_OP_RBW << FIR_OP0_SHIFT);
++ set_addr(mtd, 0, 0, 0);
++ lbc->fbcr = rest;
++ fcm->req_bytes = lbc->fbcr;
++ fcm->req_index = 0;
++ fcm->use_mdr = 0;
++ if (fcm_run_command(mtd))
++ return EFAULT;
++ return fcm_verify_buf(mtd, buf, rest);
++
++ }
++ return 0;
++}
++
++/* this function is called after Program and Erase Operations to
++ * check for success or failure */
++static int fcm_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
++{
++ volatile immap_t *im = (immap_t *) CFG_IMMR;
++ volatile lbus83xx_t *lbc= &im->lbus;
++ struct fcm_nand *fcm = this->priv;
++
++ if (fcm->status != LTESR_CC) {
++ return(0x1); /* Status Read error */
++ }
++
++ /* Use READ_STATUS command, but wait for the device to be ready */
++ fcm->use_mdr = 0;
++ fcm->req_index = 0;
++ fcm->read_bytes = 0;
++ fcm->index = 0;
++ fcm->oobbuf = -1;
++ lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) |
++ (FIR_OP_RBW << FIR%s
>>> DIFF TRUNCATED @ 16K
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