[oe-commits] org.oe.dev u-boot: add TI 1.1.4 for beagleboard and Steve's 1.3.x git version
koen commit
oe at amethyst.openembedded.net
Fri Jun 13 18:27:15 UTC 2008
u-boot: add TI 1.1.4 for beagleboard and Steve's 1.3.x git version
Author: koen at openembedded.org
Branch: org.openembedded.dev
Revision: a8fa0920a4e1dd5e47ce36f4fa80c505684b4c46
ViewMTN: http://monotone.openembedded.org/revision/info/a8fa0920a4e1dd5e47ce36f4fa80c505684b4c46
Files:
1
packages/u-boot/u-boot-git
packages/u-boot/u-boot-git/beagleboard
packages/u-boot/u-boot-omap3beagleboard-1.1.4
packages/u-boot/u-boot-git/beagleboard/armv7-a.patch
packages/u-boot/u-boot-git/beagleboard/base.patch
packages/u-boot/u-boot-git/beagleboard/name.patch
packages/u-boot/u-boot-omap3beagleboard-1.1.4/500mhz-l2enable.patch
packages/u-boot/u-boot-omap3beagleboard-1.1.4/armv7-a.patch
packages/u-boot/u-boot-omap3beagleboard-1.1.4/disable-tone-logo.patch
packages/u-boot/u-boot-omap3beagleboard-1.1.4/env.patch
packages/u-boot/u-boot-omap3beagleboard-1.1.4/name.patch
packages/u-boot/u-boot-omap3beagleboard_1.1.4.bb
packages/u-boot/u-boot_git.bb
Diffs:
#
# mt diff -r0f761bf9a1994f4bbf445420d19be2f5e8038ee2 -ra8fa0920a4e1dd5e47ce36f4fa80c505684b4c46
#
#
#
# add_dir "packages/u-boot/u-boot-git"
#
# add_dir "packages/u-boot/u-boot-git/beagleboard"
#
# add_dir "packages/u-boot/u-boot-omap3beagleboard-1.1.4"
#
# add_file "packages/u-boot/u-boot-git/beagleboard/armv7-a.patch"
# content [4bba3fab6800af92473fa2e30a214f7fe8338a96]
#
# add_file "packages/u-boot/u-boot-git/beagleboard/base.patch"
# content [2a376b51f55582cc5b5c789d00814ed2c676f152]
#
# add_file "packages/u-boot/u-boot-git/beagleboard/name.patch"
# content [84ee1a8c95077d6b7039a5b6741e3e7e4f347b3f]
#
# add_file "packages/u-boot/u-boot-omap3beagleboard-1.1.4/500mhz-l2enable.patch"
# content [0fcdb7180195146ffc05fad9dc7b8dce467d43eb]
#
# add_file "packages/u-boot/u-boot-omap3beagleboard-1.1.4/armv7-a.patch"
# content [4bba3fab6800af92473fa2e30a214f7fe8338a96]
#
# add_file "packages/u-boot/u-boot-omap3beagleboard-1.1.4/disable-tone-logo.patch"
# content [5ba0ecb76f76bc6b45121bbcc625d9a7adf8b6f9]
#
# add_file "packages/u-boot/u-boot-omap3beagleboard-1.1.4/env.patch"
# content [1e3e02a73466c1fca367543f24870b8505797e43]
#
# add_file "packages/u-boot/u-boot-omap3beagleboard-1.1.4/name.patch"
# content [7ce3313577cab5c5cf32d98787bfe166c8442d6e]
#
# add_file "packages/u-boot/u-boot-omap3beagleboard_1.1.4.bb"
# content [6cd62d1c647948e82d12b805fec5851f18b4bd0d]
#
# patch "packages/u-boot/u-boot_git.bb"
# from [e9764f3c6c5b495e1807c9f07081a24094765740]
# to [f5a6ed35ebbb55acec4098d2f8543f801d9416ab]
#
============================================================
--- packages/u-boot/u-boot-git/beagleboard/armv7-a.patch 4bba3fab6800af92473fa2e30a214f7fe8338a96
+++ packages/u-boot/u-boot-git/beagleboard/armv7-a.patch 4bba3fab6800af92473fa2e30a214f7fe8338a96
@@ -0,0 +1,11 @@
+--- u-boot/cpu/omap3/config.mk-orig 2008-05-27 16:46:45.000000000 -0700
++++ u-boot/cpu/omap3/config.mk 2008-05-29 12:50:49.000000000 -0700
+@@ -23,7 +23,7 @@
+ PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
+ -msoft-float
+
+-PLATFORM_CPPFLAGS += -march=armv7a
++PLATFORM_CPPFLAGS += -march=armv7-a
+ # =========================================================================
+ #
+ # Supply options according to compiler version
============================================================
--- packages/u-boot/u-boot-git/beagleboard/base.patch 2a376b51f55582cc5b5c789d00814ed2c676f152
+++ packages/u-boot/u-boot-git/beagleboard/base.patch 2a376b51f55582cc5b5c789d00814ed2c676f152
@@ -0,0 +1,7030 @@
+diff --git a/Makefile b/Makefile
+index cc988e1..16701c5 100644
+--- a/Makefile
++++ b/Makefile
+@@ -141,7 +141,7 @@ ifeq ($(ARCH),ppc)
+ CROSS_COMPILE = ppc_8xx-
+ endif
+ ifeq ($(ARCH),arm)
+-CROSS_COMPILE = arm-linux-
++CROSS_COMPILE = arm-none-linux-gnueabi-
+ endif
+ ifeq ($(ARCH),i386)
+ CROSS_COMPILE = i386-linux-
+@@ -252,7 +252,7 @@ LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).a
+ LIBBOARD := $(addprefix $(obj),$(LIBBOARD))
+
+ # Add GCC lib
+-PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
++PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc -lgcc_eh
+
+ # The "tools" are needed early, so put this first
+ # Don't include stuff already done in $(LIBS)
+@@ -2562,6 +2562,12 @@ SMN42_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm720t SMN42 siemens lpc2292
+
+ #########################################################################
++## ARM CORTEX Systems
++#########################################################################
++omap3530beagle_config : unconfig
++ @./mkconfig $(@:_config=) arm omap3 omap3530beagle
++
++#########################################################################
+ ## XScale Systems
+ #########################################################################
+
+diff --git a/board/omap3530beagle/Makefile b/board/omap3530beagle/Makefile
+new file mode 100644
+index 0000000..7065345
+--- /dev/null
++++ b/board/omap3530beagle/Makefile
+@@ -0,0 +1,47 @@
++#
++# (C) Copyright 2000, 2001, 2002
++# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = lib$(BOARD).a
++
++OBJS := omap3530beagle.o mem.o clock.o syslib.o sys_info.o nand.o
++SOBJS := lowlevel_init.o
++
++$(LIB): $(OBJS) $(SOBJS)
++ $(AR) crv $@ $^
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
++
++-include .depend
++
++#########################################################################
+diff --git a/board/omap3530beagle/clock.c b/board/omap3530beagle/clock.c
+new file mode 100644
+index 0000000..964525b
+--- /dev/null
++++ b/board/omap3530beagle/clock.c
+@@ -0,0 +1,316 @@
++/*
++ * (C) Copyright 2008
++ * Texas Instruments, <www.ti.com>
++ *
++ * Author :
++ * Sunil Kumar <sunilsaini05 at gmail.com>
++ * Shashi Ranjan <shashiranjanmca05 at gmail.com>
++ *
++ * Derived from Beagle Board and OMAP3 SDP code by
++ * Richard Woodruff <r-woodruff2 at ti.com>
++ * Syed Mohammed Khasim <khasim at ti.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/arch/cpu.h>
++#include <asm/io.h>
++#include <asm/arch/bits.h>
++#include <asm/arch/clocks.h>
++#include <asm/arch/clocks_omap3.h>
++#include <asm/arch/mem.h>
++#include <asm/arch/sys_proto.h>
++#include <asm/arch/sys_info.h>
++#include <environment.h>
++#include <command.h>
++
++/******************************************************************************
++ * get_sys_clk_speed() - determine reference oscillator speed
++ * based on known 32kHz clock and gptimer.
++ *****************************************************************************/
++u32 get_osc_clk_speed(void)
++{
++ u32 start, cstart, cend, cdiff, val;
++
++ val = __raw_readl(PRM_CLKSRC_CTRL);
++
++ /* If SYS_CLK is being divided by 2, remove for now */
++ val = (val & (~BIT7)) | BIT6;
++ __raw_writel(val, PRM_CLKSRC_CTRL);
++
++ /* enable timer2 */
++ val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
++ __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
++
++ /* Enable I and F Clocks for GPT1 */
++ val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
++ __raw_writel(val, CM_ICLKEN_WKUP);
++ val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
++ __raw_writel(val, CM_FCLKEN_WKUP);
++
++ __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
++ __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
++
++ /* enable 32kHz source, determine sys_clk via gauging */
++ start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
++ while (__raw_readl(S32K_CR) < start) ; /* dead loop till start time */
++ /* get start sys_clk count */
++ cstart = __raw_readl(OMAP34XX_GPT1 + TCRR);
++ /* wait for 40 cycles */
++ while (__raw_readl(S32K_CR) < (start + 20)) ;
++ cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
++ cdiff = cend - cstart; /* get elapsed ticks */
++
++ /* based on number of ticks assign speed */
++ if (cdiff > 19000)
++ return (S38_4M);
++ else if (cdiff > 15200)
++ return (S26M);
++ else if (cdiff > 13000)
++ return (S24M);
++ else if (cdiff > 9000)
++ return (S19_2M);
++ else if (cdiff > 7600)
++ return (S13M);
++ else
++ return (S12M);
++}
++
++/******************************************************************************
++ * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
++ * input oscillator clock frequency.
++ *****************************************************************************/
++void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
++{
++ if (osc_clk == S38_4M)
++ *sys_clkin_sel = 4;
++ else if (osc_clk == S26M)
++ *sys_clkin_sel = 3;
++ else if (osc_clk == S19_2M)
++ *sys_clkin_sel = 2;
++ else if (osc_clk == S13M)
++ *sys_clkin_sel = 1;
++ else if (osc_clk == S12M)
++ *sys_clkin_sel = 0;
++}
++
++/******************************************************************************
++ * prcm_init() - inits clocks for PRCM as defined in clocks.h
++ * called from SRAM, or Flash (using temp SRAM stack).
++ *****************************************************************************/
++void prcm_init(void)
++{
++ void (*f_lock_pll) (u32, u32, u32, u32);
++ int xip_safe, p0, p1, p2, p3;
++ u32 osc_clk = 0, sys_clkin_sel;
++ u32 clk_index, sil_index;
++ dpll_param *dpll_param_p;
++
++ f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
++ SRAM_VECT_CODE);
++
++ xip_safe = running_in_sram();
++
++ /* Gauge the input clock speed and find out the sys_clkin_sel
++ * value corresponding to the input clock.
++ */
++ osc_clk = get_osc_clk_speed();
++ get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
++
++ sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
++
++ /* If the input clock is greater than 19.2M always divide/2 */
++ if (sys_clkin_sel > 2) {
++ sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */
++ clk_index = sys_clkin_sel / 2;
++ } else {
++ sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */
++ clk_index = sys_clkin_sel;
++ }
++
++ /* The DPLL tables are defined according to sysclk value and
++ * silicon revision. The clk_index value will be used to get
++ * the values for that input sysclk from the DPLL param table
++ * and sil_index will get the values for that SysClk for the
++ * appropriate silicon rev.
++ */
++ sil_index = get_cpu_rev() - 1;
++ /* Unlock MPU DPLL (slows things down, and needed later) */
++ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
++ wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
++
++ /* Getting the base address of Core DPLL param table */
++ dpll_param_p = (dpll_param *) get_core_dpll_param();
++ /* Moving it to the right sysclk and ES rev base */
++ dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
++ if (xip_safe) {
++ /* CORE DPLL */
++ /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
++ sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
++ wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
++ /* For OMAP3 ES1.0 Errata 1.50, default value directly doesnt
++ work. write another value and then default value. */
++ sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */
++ sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
++ sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
++ sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
++ sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
++ sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
++ sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
++ sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
++ sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
++ sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
++ sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
++ sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
++ sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
++ sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
++ wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
++ } else if (running_in_flash()) {
++ /* if running from flash, jump to small relocated code
++ area in SRAM. */
++ p0 = __raw_readl(CM_CLKEN_PLL);
++ sr32((u32) &p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
++ sr32((u32) &p0, 4, 4, dpll_param_p->fsel); /* FREQSEL */
++
++ p1 = __raw_readl(CM_CLKSEL1_PLL);
++ sr32((u32) &p1, 27, 2, dpll_param_p->m2); /* Set M2 */
++ sr32((u32) &p1, 16, 11, dpll_param_p->m); /* Set M */
++ sr32((u32) &p1, 8, 7, dpll_param_p->n); /* Set N */
++ sr32((u32) &p1, 6, 1, 0); /* set source for 96M */
++ p2 = __raw_readl(CM_CLKSEL_CORE);
++ sr32((u32) &p2, 8, 4, CORE_SSI_DIV); /* ssi */
++ sr32((u32) &p2, 4, 2, CORE_FUSB_DIV); /* fsusb */
++ sr32((u32) &p2, 2, 2, CORE_L4_DIV); /* l4 */
++ sr32((u32) &p2, 0, 2, CORE_L3_DIV); /* l3 */
++
++ p3 = CM_IDLEST_CKGEN;
++
++ (*f_lock_pll) (p0, p1, p2, p3);
++ }
++
++ /* PER DPLL */
++ sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
++ wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
++
++ /* Getting the base address to PER DPLL param table */
++ /* Set N */
++ dpll_param_p = (dpll_param *) get_per_dpll_param();
++ /* Moving it to the right sysclk base */
++ dpll_param_p = dpll_param_p + clk_index;
++ /* Errata 1.50 Workaround for OMAP3 ES1.0 only */
++ /* If using default divisors, write default divisor + 1
++ and then the actual divisor value */
++ /* Need to change it to silicon and revision check */
++ if (1) {
++ sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2 + 1); /* set M6 */
++ sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
++ sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2 + 1); /* set M5 */
++ sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
++ sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2 + 1); /* set M4 */
++ sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
++ sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2 + 1); /* set M3 */
++ sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
++ sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2 + 1); /* set M2 */
++ sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
++ } else {
++ sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
++ sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
++ sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
++ sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
++ sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
++ }
++ sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
++ sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
++ sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */
++ sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
++ wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
++
++ /* Getting the base address to MPU DPLL param table */
++ dpll_param_p = (dpll_param *) get_mpu_dpll_param();
++ /* Moving it to the right sysclk and ES rev base */
++ dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
++ /* MPU DPLL (unlocked already) */
++ sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
++ sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
++ sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
++ sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
++ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
++ wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
++
++ /* Getting the base address to IVA DPLL param table */
++ dpll_param_p = (dpll_param *) get_iva_dpll_param();
++ /* Moving it to the right sysclk and ES rev base */
++ dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
++ /* IVA DPLL (set to 12*20=240MHz) */
++ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
++ wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDE%s
>>> DIFF TRUNCATED @ 16K
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