[oe-commits] Xerxes Rånby : llvm2.7: backported llvm2.8svn r104558, r104652 & r104653 fixes.
git version control
git at git.openembedded.org
Wed Jul 21 11:29:26 UTC 2010
Module: openembedded.git
Branch: org.openembedded.dev
Commit: de16a3d10308c81c7e40886bbe0846604eebdf77
URL: http://gitweb.openembedded.net/?p=openembedded.git&a=commit;h=de16a3d10308c81c7e40886bbe0846604eebdf77
Author: Xerxes Rånby <xerxes at zafena.se>
Date: Wed Jul 21 13:15:21 2010 +0200
llvm2.7: backported llvm2.8svn r104558, r104652 & r104653 fixes.
* llvm2.7/r104558-VFPmisc.patch: Add missing implementation
to the materialization of VFP misc. instructions
(vmrs, vmsr and vmov (immediate)).
* llvm2.7/r104652-VFPLoadStoreMultiple.patch: LLVM PR7221
Makes VFP calculations correct.
* llvm2.7/r104653-BFC-BFI.patch: LLVM PR7222
Fixes LLVM ERROR: ARMv6t2 JIT is not yet supported.
* llvm2.7_2.7.bb: Added above patches and bumped PR.
---
recipes/llvm/llvm2.7/r104558-VFPmisc.patch | 58 ++++++++++++++++++++
.../llvm2.7/r104652-VFPLoadStoreMultiple.patch | 47 ++++++++++++++++
recipes/llvm/llvm2.7/r104653-BFC-BFI.patch | 31 +++++++++++
recipes/llvm/llvm2.7_2.7.bb | 5 ++-
4 files changed, 140 insertions(+), 1 deletions(-)
diff --git a/recipes/llvm/llvm2.7/r104558-VFPmisc.patch b/recipes/llvm/llvm2.7/r104558-VFPmisc.patch
new file mode 100644
index 0000000..471ff71
--- /dev/null
+++ b/recipes/llvm/llvm2.7/r104558-VFPmisc.patch
@@ -0,0 +1,58 @@
+--- llvm/lib/Target/ARM/ARMCodeEmitter.cpp 2010/05/25 08:42:45 104587
++++ llvm/lib/Target/ARM/ARMCodeEmitter.cpp 2010/05/25 10:23:52 104588
+@@ -1465,12 +1465,55 @@
+ }
+
+ void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
++ unsigned Opcode = MI.getDesc().Opcode;
+ // Part of binary is determined by TableGn.
+ unsigned Binary = getBinaryCodeForInstr(MI);
+
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
++ switch(Opcode) {
++ default:
++ llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
++
++ case ARM::FMSTAT:
++ // No further encoding needed.
++ break;
++
++ case ARM::VMRS:
++ case ARM::VMSR: {
++ const MachineOperand &MO0 = MI.getOperand(0);
++ // Encode Rt.
++ Binary |= ARMRegisterInfo::getRegisterNumbering(MO0.getReg())
++ << ARMII::RegRdShift;
++ break;
++ }
++
++ case ARM::FCONSTD:
++ case ARM::FCONSTS: {
++ // Encode Dd / Sd.
++ Binary |= encodeVFPRd(MI, 0);
++
++ // Encode imm., Table A7-18 VFP modified immediate constants
++ const MachineOperand &MO1 = MI.getOperand(1);
++ unsigned Imm = static_cast<unsigned>(MO1.getFPImm()->getValueAPF()
++ .bitcastToAPInt().getHiBits(32).getLimitedValue());
++ unsigned ModifiedImm;
++
++ if(Opcode == ARM::FCONSTS)
++ ModifiedImm = (Imm & 0x80000000) >> 24 | // a
++ (Imm & 0x03F80000) >> 19; // bcdefgh
++ else // Opcode == ARM::FCONSTD
++ ModifiedImm = (Imm & 0x80000000) >> 24 | // a
++ (Imm & 0x007F0000) >> 16; // bcdefgh
++
++ // Insts{19-16} = abcd, Insts{3-0} = efgh
++ Binary |= ((ModifiedImm & 0xF0) >> 4) << 16;
++ Binary |= (ModifiedImm & 0xF);
++ break;
++ }
++ }
++
+ emitWordLE(Binary);
+ }
+
diff --git a/recipes/llvm/llvm2.7/r104652-VFPLoadStoreMultiple.patch b/recipes/llvm/llvm2.7/r104652-VFPLoadStoreMultiple.patch
new file mode 100644
index 0000000..6797925
--- /dev/null
+++ b/recipes/llvm/llvm2.7/r104652-VFPLoadStoreMultiple.patch
@@ -0,0 +1,47 @@
+--- llvm/lib/Target/ARM/ARMCodeEmitter.cpp 2010/05/25 10:23:52 104588
++++ llvm/lib/Target/ARM/ARMCodeEmitter.cpp 2010/05/26 00:02:28 104652
+@@ -146,11 +146,11 @@
+ return getMachineOpValue(MI, MI.getOperand(OpIdx));
+ }
+
+- /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
++ /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
+ /// machine operand requires relocation, record the relocation and return zero.
+- unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
++ unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
+ unsigned Reloc);
+- unsigned getMovi32Value(const MachineInstr &MI, unsigned OpIdx,
++ unsigned getMovi32Value(const MachineInstr &MI, unsigned OpIdx,
+ unsigned Reloc) {
+ return getMovi32Value(MI, MI.getOperand(OpIdx), Reloc);
+ }
+@@ -227,12 +227,12 @@
+ return 0;
+ }
+
+-/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
++/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
+ /// machine operand requires relocation, record the relocation and return zero.
+ unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
+- const MachineOperand &MO,
++ const MachineOperand &MO,
+ unsigned Reloc) {
+- assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
++ assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
+ && "Relocation to this function should be for movt or movw");
+
+ if (MO.isImm())
+@@ -1459,7 +1459,12 @@
+ break;
+ ++NumRegs;
+ }
+- Binary |= NumRegs * 2;
++ // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
++ // Otherwise, it will be 0, in the case of 32-bit registers.
++ if(Binary & 0x100)
++ Binary |= NumRegs * 2;
++ else
++ Binary |= NumRegs;
+
+ emitWordLE(Binary);
+ }
diff --git a/recipes/llvm/llvm2.7/r104653-BFC-BFI.patch b/recipes/llvm/llvm2.7/r104653-BFC-BFI.patch
new file mode 100644
index 0000000..763d4b4
--- /dev/null
+++ b/recipes/llvm/llvm2.7/r104653-BFC-BFI.patch
@@ -0,0 +1,31 @@
+Index: llvm-2.7/lib/Target/ARM/ARMCodeEmitter.cpp
+===================================================================
+--- llvm-2.7.orig/lib/Target/ARM/ARMCodeEmitter.cpp 2010-07-21 12:28:57.000000000 +0200
++++ llvm-2.7/lib/Target/ARM/ARMCodeEmitter.cpp 2010-07-21 12:36:04.000000000 +0200
+@@ -778,10 +778,6 @@
+ unsigned ImplicitRn) {
+ const TargetInstrDesc &TID = MI.getDesc();
+
+- if (TID.Opcode == ARM::BFC) {
+- llvm_report_error("ARMv6t2 JIT is not yet supported.");
+- }
+-
+ // Part of binary is determined by TableGn.
+ unsigned Binary = getBinaryCodeForInstr(MI);
+
+@@ -817,6 +813,15 @@
+ Binary |= ((Hi16 >> 12) & 0xF) << 16;
+ emitWordLE(Binary);
+ return;
++ } else if((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
++ uint32_t v = ~MI.getOperand(2).getImm();
++ int32_t lsb = CountTrailingZeros_32(v);
++ int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
++ // Insts[20-16] = msb, Insts[11-7] = lsb
++ Binary |= (msb & 0x1F) << 16;
++ Binary |= (lsb & 0x1F) << 7;
++ emitWordLE(Binary);
++ return;
+ }
+
+ // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
diff --git a/recipes/llvm/llvm2.7_2.7.bb b/recipes/llvm/llvm2.7_2.7.bb
index 5631f10..ef2da43 100644
--- a/recipes/llvm/llvm2.7_2.7.bb
+++ b/recipes/llvm/llvm2.7_2.7.bb
@@ -1,6 +1,6 @@
require llvm.inc
-PR = "r7"
+PR = "r8"
DEPENDS = "llvm-common llvm2.7-native"
@@ -11,7 +11,10 @@ SRC_URI = "\
http://llvm.org/releases/${PV}/llvm-${PV}.tgz \
file://arm_ppc.patch \
file://r97745-llvmPR6480.patch \
+ file://r104558-VFPmisc.patch \
file://r104587-MOVimm32.patch \
+ file://r104652-VFPLoadStoreMultiple.patch \
+ file://r104653-BFC-BFI.patch \
file://rawMOVLRPC.patch \
"
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