[oe-commits] Khem Raj : cross-canadian.bbclass: Recognise musl

[git at git.openembedded.org]

Module: openembedded-core.git
Branch: master-next
Commit: 7e5f2a03dfc14fd93280e7e13369c07cf3aa7f22
URL:    http://git.openembedded.org/?p=openembedded-core.git&a=commit;h=7e5f2a03dfc14fd93280e7e13369c07cf3aa7f22

Author: Khem Raj <raj.khem at gmail.com>
Date:   Thu May 29 00:01:05 2014 -0700

cross-canadian.bbclass: Recognise musl

Signed-off-by: Khem Raj <raj.khem at gmail.com>
Signed-off-by: Richard Purdie <richard.purdie at linuxfoundation.org>

---

 meta/classes/cross-canadian.bbclass | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/meta/classes/cross-canadian.bbclass b/meta/classes/cross-canadian.bbclass
index cea6afb..25e246d 100644
--- a/meta/classes/cross-canadian.bbclass
+++ b/meta/classes/cross-canadian.bbclass
@@ -27,7 +27,9 @@ python () {
     tarch = d.getVar("TARGET_ARCH", True)
     if tarch == "powerpc":
         tos = d.getVar("TARGET_OS", True)
-        if (tos != "linux" and tos != "linux-gnuspe" and tos != "linux-uclibc" and tos != "linux-uclibcspe"):
+        if (tos != "linux" and tos != "linux-gnuspe"
+            and tos != "linux-uclibc" and tos != "linux-uclibcspe"
+            and tos != "linux-musl" and tos != "linux-muslspe"):
             bb.fatal("Building cross-candian powerpc for an unknown TARGET_SYS (%s), please update cross-canadian.bbclass" % d.getVar("TARGET_SYS", True))
         # This is a bit ugly. We need to zero LIBC/ABI extension which will change TARGET_OS
         # however we need the old value in some variables. We expand those here first.