[OE-core] [PATCH] x264: add textrel to INSANE_SKIP for cyclone5 machine

[sujith h]

On Thu, Sep 15, 2016 at 10:13 AM, sujith h <sujith.h at gmail.com> wrote:

>
>
> On Thu, Sep 15, 2016 at 4:41 AM, Burton, Ross <ross.burton at intel.com>
> wrote:
>
>>
>> On 12 September 2016 at 07:13, Sujith H <sujith.h at gmail.com> wrote:
>>
>>> +# PIC can't be enabled for 32-bit x86 and cyclone5
>>>  INSANE_SKIP_${PN}_append_x86 = " textrel"
>>> +INSANE_SKIP_${PN}_append_cyclone5 = " textrel"
>>>
>>
>> Can this be generalised or is it absolutely specific to cyclone5?  If it
>> can't be generalised then I feel that this should belong in the cyclone5
>> BSP.
>>
>
> We found this with cyclone5 BSP. I will try to figure out how if we can
> see it with qemuarm or other BSP's too.
>

I tried with qemuarm, it wasn't reproducible. But with imx6qsabresd from
meta-fsl-arm, it was reproducible. So I believe we can generalize this
patch. I will send the updated one shortly. Thanks for the pointer Ross.


>
>>
>> Ross
>>
>
>
>
> --
> സുജിത് ഹരിദാസന്
> Bangalore
> <Project>Contributor to KDE project
> <Project>Contributor to Yocto project
> http://fci.wikia.com/wiki/Anti-DRM-Campaign
> <Blog> http://sujithh.info
> C-x C-c
>



-- 
സുജിത് ഹരിദാസന്
Bangalore
<Project>Contributor to KDE project
<Project>Contributor to Yocto project
http://fci.wikia.com/wiki/Anti-DRM-Campaign
<Blog> http://sujithh.info
C-x C-c
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