[OE-core] [PATCH 0/4] Recipes for Open Source Verilog and Lattice iCE40 FPGAs tools

[Nathan Rossi]

On 14 September 2017 at 22:56, Nathan Rossi <nathan at nathanrossi.com> wrote:
> On 13 September 2017 at 11:24, Khem Raj <raj.khem at gmail.com> wrote:
>> On Tue, Sep 12, 2017 at 4:42 PM, Trevor Woerner <twoerner at gmail.com> wrote:
>>> On Tue, Sep 12, 2017 at 4:21 PM, Khem Raj <raj.khem at gmail.com> wrote:
>>>> On Mon, Sep 11, 2017 at 1:58 AM, Burton, Ross <ross.burton at intel.com> wrote:
>>>>> On 10 September 2017 at 14:14, Nathan Rossi <nathan at nathanrossi.com> wrote:
>>>>>>
>>>>>> Please note whilst this series is sent for oe-core it may be better
>>>>>> located in another layer? (e.g. meta-oe). However since the recipes and
>>>>>> the tools they build are not specific to a single BSP it did not make
>>>>>> sense to keep in a BSP specific layer.
>>>>>
>>>>>
>>>>> Sounds like a dedicated FPGA layer would be ideal.
>>>>>
>>>>
>>>> I think a layer for 2 recipes might be too much. Put it under recipes-devtools
>>>> in meta-oe for now.
>>>
>>> 5?
>>>
>>> Am I reading this patch correctly? There are 5 recipes?
>>
>> 2 or 5 doesnt matter I just meant "too few to be a layer of its own"
>> engineers minds :)
>
> That was my initial thoughts, and I was following your suggestion Khem :).
>
> Though it seems like now is probably a reasonable time as any to
> create a layer to give a home for recipes in the HDL/FPGA space. After
> all there are other projects that I would like to look at and probably
> create recipes for in time, so what is now 5 recipes is likely to
> increase.
>
> But I don't like the idea of a FPGA or vendor (e.g. lattice/etc)
> specific layer since that makes it appear like a BSP layer, and there
> is the problem of the tools 'conflicting' with proprietary tools those
> vendors provide. I was thinking of following the approach of a
> language-like layer similar to how meta-python/meta-rust/etc. are
> setup, something like meta-hdl? Which would cover the recipes in the
> language space (simulation/high-level hdl) as well as the recipes that
> translate/compile HDLs for physical targets (FPGA, CPLD, etc).

For those interested, I have setup a meta-hdl layer and published it
on github, it includes all the recipes from this patch series.

https://github.com/nathanrossi/meta-hdl

I've also submitted it to the layer index.

Regards,
Nathan