[OE-core] [PATCH] gstreamer: Add RISC-V support

[Khem Raj]

On Tue, Jan 8, 2019 at 4:19 PM Alistair Francis
<Alistair.Francis at wdc.com> wrote:
>
> Backport RISC-V support from master Gstreamer.
>
> Signed-off-by: Alistair Francis <alistair.francis at wdc.com>
> ---
>  ...stconfig.h.in-initial-RISC-V-support.patch | 28 +++++++++++++++++++
>  .../gstreamer/gstreamer1.0_1.14.4.bb          |  3 ++
>  2 files changed, 31 insertions(+)
>  create mode 100644 meta/recipes-multimedia/gstreamer/files/0002-gstconfig.h.in-initial-RISC-V-support.patch
>
> diff --git a/meta/recipes-multimedia/gstreamer/files/0002-gstconfig.h.in-initial-RISC-V-support.patch b/meta/recipes-multimedia/gstreamer/files/0002-gstconfig.h.in-initial-RISC-V-support.patch
> new file mode 100644
> index 0000000000..8d8f8dca00
> --- /dev/null
> +++ b/meta/recipes-multimedia/gstreamer/files/0002-gstconfig.h.in-initial-RISC-V-support.patch
> @@ -0,0 +1,28 @@
> +From 8a156d1725ecd03f2e8cdc8874e081dda2d3b43d Mon Sep 17 00:00:00 2001
> +From: Aurelien Jarno <aurelien at aurel32.net>
> +Date: Sun, 15 Apr 2018 00:49:55 +0200
> +Subject: [PATCH] gstconfig.h.in: initial RISC-V support
> +
> +RISC-V supports unaligned accesses, but these might run extremely slowly
> +depending on the implementation. Therefore set GST_HAVE_UNALIGNED_ACCESS
> +to 0 on this architecture.
> +
> +https://bugzilla.gnome.org/show_bug.cgi?id=795271
> +Upstream-Status: Accepted [1.15.1 - https://bugzilla.gnome.org/show_bug.cgi?id=795271]
> +---
> + gst/gstconfig.h.in | 2 +-
> + 1 file changed, 1 insertion(+), 1 deletion(-)
> +
> +diff --git a/gst/gstconfig.h.in b/gst/gstconfig.h.in
> +index 6351c04da..33dfed1f6 100644
> +--- a/gst/gstconfig.h.in
> ++++ b/gst/gstconfig.h.in
> +@@ -104,7 +104,7 @@
> +  * http://docs.oracle.com/cd/E19205-01/820-4155/c++_faq.html#Vers6
> +  * https://software.intel.com/en-us/node/583402
> +  */
> +-#if defined(__alpha__) || defined(__arc__) || defined(__arm__) || defined(__aarch64__) || defined(__bfin) || defined(__hppa__) || defined(__nios2__) || defined(__MICROBLAZE__) || defined(__mips__) || defined(__or1k__) || defined(__sh__) || defined(__SH4__) || defined(__sparc__) || defined(__sparc) || defined(__ia64__) || defined(_M_ALPHA) || defined(_M_ARM) || defined(_M_IA64) || defined(__xtensa__) || defined(__e2k__)
> ++#if defined(__alpha__) || defined(__arc__) || defined(__arm__) || defined(__aarch64__) || defined(__bfin) || defined(__hppa__) || defined(__nios2__) || defined(__MICROBLAZE__) || defined(__mips__) || defined(__or1k__) || defined(__sh__) || defined(__SH4__) || defined(__sparc__) || defined(__sparc) || defined(__ia64__) || defined(_M_ALPHA) || defined(_M_ARM) || defined(_M_IA64) || defined(__xtensa__) || defined(__e2k__) || defined(__riscv)
> + #  define GST_HAVE_UNALIGNED_ACCESS 0
> + #elif defined(__i386__) || defined(__i386) || defined(__amd64__) || defined(__amd64) || defined(__x86_64__) || defined(__ppc__) || defined(__ppc64__) || defined(__powerpc__) || defined(__powerpc64__) || defined(__m68k__) || defined(_M_IX86) || defined(_M_AMD64) || defined(_M_X64) || defined(__s390__) || defined(__s390x__) || defined(__zarch__)
> + #  define GST_HAVE_UNALIGNED_ACCESS 1
> diff --git a/meta/recipes-multimedia/gstreamer/gstreamer1.0_1.14.4.bb b/meta/recipes-multimedia/gstreamer/gstreamer1.0_1.14.4.bb
> index 232234b888..c3bac1f658 100644
> --- a/meta/recipes-multimedia/gstreamer/gstreamer1.0_1.14.4.bb
> +++ b/meta/recipes-multimedia/gstreamer/gstreamer1.0_1.14.4.bb
> @@ -30,6 +30,9 @@ SRC_URI = " \
>  SRC_URI[md5sum] = "f67fbbc42bd85a0701df119f52fb52bd"
>  SRC_URI[sha256sum] = "f94f6696c5f05a3b3a9183e39c5f5c0b779f75a04c0efa497e7920afa985ffc7"
>
> +SRC_URI_append_riscv64 = " file://0002-gstconfig.h.in-initial-RISC-V-support.patch"
> +SRC_URI_append_riscv32 = " file://0002-gstconfig.h.in-initial-RISC-V-support.patch"
> +

there is nothing riscv specific here. This patch should be applied
unconditionally.

>  PACKAGECONFIG ??= "${@bb.utils.contains('PTEST_ENABLED', '1', 'tests', '', d)} \
>                     "
>
> --
> 2.19.1
>
> --
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