[OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

[Khem Raj]

On Wed, Nov 6, 2019 at 1:34 PM Alistair Francis
<Alistair.Francis at wdc.com> wrote:
>
> On Wed, 2019-11-06 at 12:54 -0800, Khem Raj wrote:
> > On Wed, Nov 6, 2019 at 12:37 PM Alistair Francis
> > <alistair.francis at wdc.com> wrote:
> > > Signed-off-by: Alistair Francis <alistair.francis at wdc.com>
> > > ---
> > >  meta/conf/machine/include/riscv/arch-riscv.inc |  3 ++-
> > >  meta/conf/machine/include/riscv/tune-riscv.inc | 17
> > > +++++++++++++++--
> > >  2 files changed, 17 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc
> > > b/meta/conf/machine/include/riscv/arch-riscv.inc
> > > index f3edcc39f7..6737545e00 100644
> > > --- a/meta/conf/machine/include/riscv/arch-riscv.inc
> > > +++ b/meta/conf/machine/include/riscv/arch-riscv.inc
> > > @@ -4,7 +4,8 @@ DEFAULTTUNE ?= "riscv64"
> > >
> > >  TUNE_ARCH = "${TUNE_ARCH_tune-${DEFAULTTUNE}}"
> > >  TUNE_PKGARCH = "${TUNE_PKGARCH_tune-${DEFAULTTUNE}}"
> > > -TUNE_CCARGS .= ""
> > > +TUNE_CCARGS_riscv64 .= "${@bb.utils.contains('TUNE_FEATURES',
> > > 'riscv64-f', ' -mabi=lp64d', ' -mabi=lp64', d)}"
> > > +TUNE_CCARGS_riscv32 .= "${@bb.utils.contains('TUNE_FEATURES',
> > > 'riscv32-f', ' -mabi=ilp32f', ' -mabi=ilp32', d)}"
> > >
> > >  # QEMU usermode fails with invalid instruction error (For riscv32)
> > >  MACHINE_FEATURES_BACKFILL_CONSIDERED_append = "
> > > ${@bb.utils.contains('TUNE_FEATURES', 'riscv32', ' qemu-usermode',
> > > '', d)}"
> > > diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc
> > > b/meta/conf/machine/include/riscv/tune-riscv.inc
> > > index 25d0463492..631653f2a2 100644
> > > --- a/meta/conf/machine/include/riscv/tune-riscv.inc
> > > +++ b/meta/conf/machine/include/riscv/tune-riscv.inc
> > > @@ -1,12 +1,26 @@
> > >  require conf/machine/include/riscv/arch-riscv.inc
> > >
> > >  TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations"
> > > +TUNEVALID[riscv64-f] = "Enable 64-bit RISC-V optimizations with
> > > hard float"
> > >  TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations"
> > > +TUNEVALID[riscv32-f] = "Enable 32-bit RISC-V optimizations with
> > > hard float"
> > >
> > >  TUNEVALID[bigendian] = "Big endian mode"
> > >
> > > -AVAILTUNES += "riscv64 riscv32"
> > > +AVAILTUNES += "riscv64 riscv64-f riscv32 riscv32-f"
> > >
> > > +# Hard float
> > > +TUNE_FEATURES_tune-riscv64-f = "${TUNE_FEATURES_tune-riscv64}
> > > riscv64-f"
> > > +TUNE_ARCH_tune-riscv64-f = "riscv64"
> > > +TUNE_PKGARCH_tune-riscv64-f = "riscv64"
> > > +PACKAGE_EXTRA_ARCHS_tune-riscv64-f = "riscv64"
> > > +
> > > +TUNE_FEATURES_tune-riscv32-f = "${TUNE_FEATURES_tune-riscv32}
> > > riscv32-f"
> > > +TUNE_ARCH_tune-riscv32-f = "riscv32"
> > > +TUNE_PKGARCH_tune-riscv32-f = "riscv32"
> > > +PACKAGE_EXTRA_ARCHS_tune-riscv32-f = "riscv32"
> > > +
> > > +# Soft float
> > >  TUNE_FEATURES_tune-riscv64 = "riscv64"
> > >  TUNE_ARCH_tune-riscv64 = "riscv64"
> > >  TUNE_PKGARCH_tune-riscv64 = "riscv64"
> > > @@ -16,4 +30,3 @@ TUNE_FEATURES_tune-riscv32 = "riscv32"
> > >  TUNE_ARCH_tune-riscv32 = "riscv32"
> > >  TUNE_PKGARCH_tune-riscv32 = "riscv32"
> > >  PACKAGE_EXTRA_ARCHS_tune-riscv32 = "riscv32"
> > > -
> >
> >  its better to add riscv64sf and keep existing tunes as it is. since
> > sf is going to be rare
> > compared to rv64gc
>
> Ok, these are the tunes I have now:
>     riscv64 riscv64sf riscv32 riscv32hf

what would riscv32hf be ?

>
> Alistair
>
> >
> > > --
> > > 2.23.0
> > >
> > > --
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