[OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

[Adrian Bunk]

On Sat, Nov 09, 2019 at 10:05:22PM +0000, Richard Purdie wrote:
> On Sat, 2019-11-09 at 22:30 +0200, Adrian Bunk wrote:
> > On Fri, Nov 08, 2019 at 11:07:04PM +0000, Richard Purdie wrote:
> > > On Fri, 2019-11-08 at 22:24 +0200, Adrian Bunk wrote:
> > > > Especially when looking at the arm64 situation I am wondering
> > > > whether the best option might be to throw away the tunes mess and
> > > > let
> > > > the user write the compiler options directly.
> > > 
> > > OE once did that. I think anyone who lived through it would say
> > > that
> > > the current situation *is* an improvement over a free-for-all.
> > > 
> > > This is mainly as at least we're now consistent whereas before the
> > > same
> > > thing had different names in each BSP.
> > 
> > The BSPs should not invent names for anything, all a BSP should do
> > would be to set some kind of
> >   TARGET_CFLAGS += "-mcpu=cortex-a53+crc+crypto+sm4+nosimd"
> 
> What is the name of the package feed these binaries would go into?

The name of whatever is passed to the compiler,
or an artificial name chosen by the distribution.

> > > I don't know what the answer is but I don't want to go back to
> > > that!
> > 
> > As of gcc 9 there are for arm64[1]:
> > 
> > 6 -march= architecture levels (8.0 to 8.5)
> > 35 -mtune= tune options
> > 22 modifiers for -march= and -mtune=
> > 3 different ABIs (aarch64, aarch64-ilp32, armv7)
> > 
> > Even ignoring the tunes you already have
> >   6 * 2^22
> > different architecture+modifier combinations.
> > 
> > Not all combinations are valid, but another can of worms are the
> > definitions what is valid and what is default amd what gets
> > indirectly
> > enabled, e.g.
> >   fp16fml
> >     Enable FP16 fmla extension. This also enables FP16 extensions
> > and 
> >     floating-point instructions. This option is enabled by default
> > for 
> >     -march=armv8.4-a. Use of this option with architectures prior to 
> >     Armv8.2-A is not supported.
> > 
> > It can be recursive:
> >   Feature crypto implies aes, sha2, and simd, which implies fp. 
> >   Conversely, nofp implies nosimd, which implies nocrypto, noaes and
> > nosha2. 
> 
> I'd advocate that we add the combinations which people need and use.
> The tune structure doesn't require every combination be there.

Does any person volunteer to be the "we"?

This is nothing that will just work, and for arm64 we are talking about 
30+ tune file each with a sizeable number of tune combintations.

The few tunes that currently exist do not even expose the fact that
there are already 6 architecture levels with one-way compatibility.

And how do you determine "combinations which people need and use"?

It is up to the SoC designer which features to buy from ARM,
and new combinations appear all the time.

Like how will it work in practice if a user asks today for a tune for
a Cortex A55 without sha3 but with sm4 enabled for warrior?

I understand what you want, but I am worried that in practice this might
just be a huge mess.

And it is a lot more complex than the few combinations currently
available on RISC-V.

> Cheers,
> 
> Richard

cu
Adrian

-- 

       "Is there not promise of rain?" Ling Tan asked suddenly out
        of the darkness. There had been need of rain for many days.
       "Only a promise," Lao Er said.
                                       Pearl S. Buck - Dragon Seed