<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Sat, Mar 12, 2016 at 9:43 AM, Richard Purdie <span dir="ltr"><<a href="mailto:richard.purdie@linuxfoundation.org" target="_blank">richard.purdie@linuxfoundation.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="HOEnZb"><div class="h5">On Fri, 2016-03-11 at 13:44 -0500, Bruce Ashfield wrote:<br>
> Importing a series of mainline backports to support USB on a couple<br>
> of<br>
> Intel platforms:<br>
><br>
> bbce8fe2cc42 usb: dwc3: pci: add support for Intel Broxton SOC<br>
> e734e1d9f827 usb: dwc3: pci: Set enblslpm quirk for Synopsys<br>
> platforms<br>
> 1c6bb6694d50 usb: dwc3: Add dis_enblslpm_quirk<br>
> 1c6be99e56b8 usb: dwc3: pci: trivial: Formatting<br>
> 2f2b89764b97 usb: dwc3: pci: passing forward the ACPI companion<br>
> ea4b3c72d976 usb: dwc3: core: convert to unified device property<br>
> interface<br>
> dc670b52c69a usb: common: of_usb_get_dr_mode to usb_get_dr_mode<br>
> 586fc5174649 usb: dwc3: st: prepare the driver for generic<br>
> usb_get_dr_mode function<br>
> 0624bd9af7ef usb: common: of_usb_get_maximum_speed to<br>
> usb_get_maximum_speed<br>
> e65bc5467e07 usb: dwc3: Add frame length adjustment quirk<br>
> a90954c5d267 usb: musb: dsps: control musb speed based on dts<br>
> setting<br>
> b48ff160a993 usb: renesas_usbhs: Allow an OTG PHY driver to<br>
> provide VBUS<br>
> d1c59752195e usb: chipidea: set usb otg capabilities<br>
> 733eada2cdec usb: common: add API to update usb otg capabilities<br>
> by device tree<br>
> 7ab2108dd82b usb: dwc3: core: avoid NULL pointer dereference<br>
> 1aedb48b7dc9 usb: dwc3: add ULPI interface support<br>
> 07e42a29fb7e usb: dwc3: pci: add quirk for Baytrails<br>
> 065917252622 usb: dwc3: add hsphy_interface property<br>
> b2bb32a363a3 usb: dwc3: setup phys earlier<br>
> bf6bb0a6ebb5 usb: dwc3: soft reset to it's own function<br>
> d481da949476 usb: dwc3: cache hwparams earlier<br>
> 9ac66262a201 usb: dwc3: store driver data earlier<br>
> 5f940588938c usb: dwc3: ULPI or UTMI+ select<br>
> 04fdce097f83 usb: dwc3: USB2 PHY register access bits<br>
> b7209213cc05 usb: add bus type for USB ULPI<br>
<br>
</div></div>I have a suspicion this breaks qemuppc:<br>
<br>
<a href="https://autobuilder.yoctoproject.org/main/builders/nightly-ppc-lsb/builds/683/steps/BuildImages/logs/stdio" rel="noreferrer" target="_blank">https://autobuilder.yoctoproject.org/main/builders/nightly-ppc-lsb/builds/683/steps/BuildImages/logs/stdio</a></blockquote><div><br></div><div>Yup. With mainline backports, I have a shorter validation cycle, since they really should</div><div>be safe.</div><div><br></div><div>I'll hunt up whatever is missing from the series and send another update.</div><div><br></div><div>Bruce</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br>
<br>
Cheers,<br>
<br>
Richard<br>
<div class="HOEnZb"><div class="h5">--<br>
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</div></div></blockquote></div><br><br clear="all"><div><br></div>-- <br><div class="gmail_signature">"Thou shalt not follow the NULL pointer, for chaos and madness await thee at its end"</div>
</div></div>