<div><br></div><div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, Sep 24, 2019 at 6:09 PM Alistair Francis <<a href="mailto:alistair23@gmail.com">alistair23@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">I raised the regression on the QEMU mailing list while I was preparing<br>
the revert for QEMU and Palmer pointed out this diff for musl:<br>
<br>
diff --git a/arch/riscv64/atomic_arch.h b/arch/riscv64/atomic_arch.h<br>
index c9765342..41ad4d04 100644<br>
--- a/arch/riscv64/atomic_arch.h<br>
+++ b/arch/riscv64/atomic_arch.h<br>
@@ -14,7 +14,7 @@ static inline int a_cas(volatile int *p, int t, int s)<br>
" sc.w.aqrl %1, %4, (%2)\n"<br>
" bnez %1, 1b\n"<br>
"1:"<br>
- : "=&r"(old), "=r"(tmp)<br>
+ : "=&r"(old), "=&r"(tmp)<br>
: "r"(p), "r"(t), "r"(s)<br>
: "memory");<br>
return old;<br>
@@ -31,7 +31,7 @@ static inline void *a_cas_p(volatile void *p, void<br>
*t, void *s)<br>
" sc.d.aqrl %1, %4, (%2)\n"<br>
" bnez %1, 1b\n"<br>
"1:"<br>
- : "=&r"(old), "=r"(tmp)<br>
+ : "=&r"(old), "=&r"(tmp)<br>
: "r"(p), "r"(t), "r"(s)<br>
: "memory");<br>
return old;<br>
<br>
This seems to fix the problem for me. Hopefully Palmer will prepare a<br>
patch then we can just cherry pick that (from the list) on musl in OE<br>
core.<br>
<br>
I'm not going to send out the QEMU revert patch.<br>
</blockquote><div dir="auto"><br></div><div dir="auto">This is fine I think we were discussing atomics at musl IRC I will take this patch to discussions </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br>
Alistair<br>
<br>
On Mon, Sep 23, 2019 at 10:12 PM Khem Raj <<a href="mailto:raj.khem@gmail.com" target="_blank">raj.khem@gmail.com</a>> wrote:<br>
><br>
> Please send a patch<br>
><br>
> On Mon, Sep 23, 2019 at 9:58 PM Alistair Francis <<a href="mailto:alistair23@gmail.com" target="_blank">alistair23@gmail.com</a>> wrote:<br>
> ><br>
> > On Mon, Sep 23, 2019 at 7:11 PM Khem Raj <<a href="mailto:raj.khem@gmail.com" target="_blank">raj.khem@gmail.com</a>> wrote:<br>
> > ><br>
> > > On Mon, Sep 23, 2019 at 6:39 PM Alistair Francis<br>
> > > <<a href="mailto:Alistair.Francis@wdc.com" target="_blank">Alistair.Francis@wdc.com</a>> wrote:<br>
> > > ><br>
> > > > On Mon, 2019-09-23 at 17:59 -0700, Alistair Francis wrote:<br>
> > > > > On Mon, Sep 23, 2019 at 3:40 PM Khem Raj <<a href="mailto:raj.khem@gmail.com" target="_blank">raj.khem@gmail.com</a>> wrote:<br>
> > > > > > Alistair,<br>
> > > > > ><br>
> > > > > > OE-core qemu upgrade to 4.1 has ended up with regressing musl/riscv<br>
> > > > > > port. I could pin point it to<br>
> > > > > ><br>
> > > > > > <a href="https://git.openembedded.org/openembedded-core/commit/?id=50a7dec95618080962e56fd347f505e691b7ad6f" rel="noreferrer" target="_blank">https://git.openembedded.org/openembedded-core/commit/?id=50a7dec95618080962e56fd347f505e691b7ad6f</a><br>
> > > > > ><br>
> > > > > > it works fine with 4.0, I havent looked further<br>
> > > > > ><br>
> > > > > > To reproduce<br>
> > > > > ><br>
> > > > > > build<br>
> > > > > > MACHINE=qemuriscv64 TCLIBC=musl bitbake core-image-minimal<br>
> > > > > > TCLIBC=musl runqemu nographic<br>
> > > > ><br>
> > > > > Thanks, I can reproduce this and am bisecting QEMU now.<br>
> > > ><br>
> > > > This QEMU patch causes the failure. It reverts cleanly on master and<br>
> > > > that fixes the issue:<br>
> > > ><br>
> > > > RISC-V: Clear load reservations on context switch and SC<br>
> > > ><br>
> > > > This prevents a load reservation from being placed in one<br>
> > > > context/process,<br>
> > > > then being used in another, resulting in an SC succeeding incorrectly<br>
> > > > and<br>
> > > > breaking atomics.<br>
> > > ><br>
> > > > Signed-off-by: Joel Sing <<a href="mailto:joel@sing.id.au" target="_blank">joel@sing.id.au</a>><br>
> > > > Reviewed-by: Palmer Dabbelt <<a href="mailto:palmer@sifive.com" target="_blank">palmer@sifive.com</a>><br>
> > > > Reviewed-by: Richard Henderson <<a href="mailto:richard.henderson@linaro.org" target="_blank">richard.henderson@linaro.org</a>><br>
> > > > Signed-off-by: Palmer Dabbelt <<a href="mailto:palmer@sifive.com" target="_blank">palmer@sifive.com</a>><br>
> > > ><br>
> > > > I'll investigate a full solution tomorrow, in the mean time do you want<br>
> > > > to just revert the patch?<br>
> > ><br>
> > > yes lets use the revert for now, this will give you enough time to<br>
> > > investigate solution<br>
> > > since its riscv specific it will be low risk and we can even go to 3.0<br>
> > > release with it<br>
> ><br>
> > Do you want me to prepare a patch or do you want to do it?<br>
> ><br>
> > Alistair<br>
> ><br>
> > ><br>
> > > ><br>
> > > > Alistair<br>
> > > ><br>
> > > > ><br>
> > > > > Alistair<br>
> > > > ><br>
> > > > > > Thanks<br>
> > > > > > -Khem<br>
> > > > > > --<br>
> > > > > > _______________________________________________<br>
> > > > > > Openembedded-core mailing list<br>
> > > > > > <a href="mailto:Openembedded-core@lists.openembedded.org" target="_blank">Openembedded-core@lists.openembedded.org</a><br>
> > > > > > <a href="http://lists.openembedded.org/mailman/listinfo/openembedded-core" rel="noreferrer" target="_blank">http://lists.openembedded.org/mailman/listinfo/openembedded-core</a><br>
</blockquote></div></div>