[oe] [STABLE] it is possible to add 600Mhz for kernel for beagleboard revB7 (OMAP3430 ES3.0) ?

Raffaele Recalcati lamiaposta71 at gmail.com
Tue Apr 14 11:06:57 UTC 2009


openembedded commit 31c5753ea1a29750060a002b867362354ae42669

Looking at kernel 2.6.28-r25 messages I see:

Uncompressing Linux.............................................................................................................................................................................
done, booting the kernel.
Linux version 2.6.28-omap1 (recalcati at recalcati-laptop) (gcc version
4.3.1 (GCC) ) #1 Sat Apr 11 14:16:14 CEST 2009
CPU: ARMv7 Processor [411fc083] revision 3 (ARMv7), cr=10c5387f
CPU: VIPT nonaliasing data cache, VIPT nonaliasing instruction cache
Machine: OMAP3 Beagle Board
Memory policy: ECC disabled, Data cache writeback
OMAP3430 ES3.0
SRAM: Mapped pa 0x40200000 to va 0xd7000000 size: 0x100000
Reserving 15728640 bytes SDRAM for VRAM
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 32512
Kernel command line: console=ttyS2,115200n8 root=/dev/mmcblk0p2
rootwait rw init=/init omapfb.video_mode=hd720 omapfb.debug=y
omap-dss.def_disp=lcd omap-dss.debug=y
Clocking rate (Crystal/DPLL/ARM core): 26.0/332/500 MHz
GPMC revision 5.0
IRQ: Found an INTC at 0xd8200000 (revision 4.0) with 96 interrupts
Total of 96 interrupts on 1 active controller
OMAP34xx GPIO hardware version 2.5
PID hash table entries: 512 (order: 9, 2048 bytes)
OMAP clockevent source: GPTIMER12 at 32768 Hz

It is possible to add 600Mhz rate?
I looked inside arch/arm/mach-omap2/clock34xx.c,
but there is something to do:

       /* REVISIT: Not yet ready for OMAP3 */
#if 0
       /* Check the MPU rate set by bootloader */
       clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
       for (prcm = rate_table; prcm->mpu_speed; prcm++) {
               if (!(prcm->flags & cpu_mask))
                       continue;
               if (prcm->xtal_speed != sys_ck.rate)
                       continue;
               if (prcm->dpll_speed <= clkrate)
                        break;
       }
       curr_prcm_set = prcm;
#endif

       recalculate_root_clocks();

       printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
              "%ld.%01ld/%ld/%ld MHz\n",
              (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
              (core_ck.rate / 1000000), (arm_fck.rate / 1000000));


Any help?




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