[oe] [PATCH] linux-libc-headers_nios2-2.6.28: nios2 fork.
Leon Woestenberg
leon.woestenberg at gmail.com
Sun Dec 6 22:44:50 UTC 2009
Tested-by: Walter Goossens <walter.goossens at axon.tv>
Tested-by: Leon Woestenberg <leon at sidebranch.com>
Signed-off-by: Leon Woestenberg <leon at sidebranch.com>
---
.../headless_hwselect.patch | 120 +
.../linux-libc-headers-nios2-2.6.28/procinfo.h | 24 +
.../linux-libc-headers-nios2-2.6.28/system.ptf | 3492 ++++++++++++++++++++
3 files changed, 3636 insertions(+), 0 deletions(-)
create mode 100644 recipes/linux-libc-headers/linux-libc-headers-nios2-2.6.28/headless_hwselect.patch
create mode 100644 recipes/linux-libc-headers/linux-libc-headers-nios2-2.6.28/procinfo.h
create mode 100755 recipes/linux-libc-headers/linux-libc-headers-nios2-2.6.28/system.ptf
diff --git a/recipes/linux-libc-headers/linux-libc-headers-nios2-2.6.28/headless_hwselect.patch b/recipes/linux-libc-headers/linux-libc-headers-nios2-2.6.28/headless_hwselect.patch
new file mode 100644
index 0000000..3029f69
--- /dev/null
+++ b/recipes/linux-libc-headers/linux-libc-headers-nios2-2.6.28/headless_hwselect.patch
@@ -0,0 +1,120 @@
+diff -urPN nios2-linux-test-dm/linux-2.6/arch/nios2/Makefile nios2-linux/linux-2.6/arch/nios2/Makefile
+--- nios2-linux-test-dm/linux-2.6/arch/nios2/Makefile 2009-07-30 10:27:19.000000000 +0000
++++ nios2-linux/linux-2.6/arch/nios2/Makefile 2009-08-17 15:07:40.000000000 +0000
+@@ -134,7 +134,8 @@
+ mkdir -p $(dir $(objtree)/$(HARDWARE_MK)); \
+ perl -I$(TOPDIR)/arch/$(ARCH)/scripts \
+ $(srctree)/arch/$(ARCH)/scripts/hwselect.pl $(SYSPTF) \
+- $(objtree)/$(HARDWARE_MK)
++ $(objtree)/$(HARDWARE_MK) \
++ $(CPU_SELECTION) $(MEM_SELECTION)
+ endef
+
+ .PHONY: hwselect
+diff -urPN nios2-linux-test-dm/linux-2.6/arch/nios2/scripts/hwselect.pl nios2-linux/linux-2.6/arch/nios2/scripts/hwselect.pl
+--- nios2-linux-test-dm/linux-2.6/arch/nios2/scripts/hwselect.pl 2009-07-30 10:27:19.000000000 +0000
++++ nios2-linux/linux-2.6/arch/nios2/scripts/hwselect.pl 2009-08-17 15:05:45.000000000 +0000
+@@ -14,6 +14,10 @@
+ my $index;
+ my $system;
+
++my $cpu_selection;
++my $cpu_index = -1;
++my $mem_selected;
++my $mem_index = -1;
+ #
+ # Subroutine: Prompt user for an answer
+ #
+@@ -36,8 +40,12 @@
+ #
+ # Check for correct number of args
+ #
+-
+-if (scalar (@ARGV) != 2) {
++if (scalar (@ARGV) == 4) {
++ $ptf_filename = $ARGV[0];
++ $target_filename = $ARGV[1];
++ $cpu_index = $ARGV[2];
++ $mem_index = $ARGV[3];
++} elsif (scalar (@ARGV) != 2) {
+ print STDERR "ERROR: Invalid number of parameters.\n";
+ exit;
+ } else {
+@@ -67,27 +75,37 @@
+ # Grab listing of Nios II processors and force user to select one:
+ #
+
+-print "\n--- Please select which CPU you wish to build the kernel against:\n\n";
+-
+ my @cpulist = $system->getCPUList ('altera_nios2');
+-my %cpuinfo;
+-
+-$index = 1;
+-foreach my $cpu (@cpulist) {
+- my $cpu_module = $system->getCPU ($cpu);
+- if ($cpu_module->isEnabled ()) {
+- my $class = $cpu_module->getClass();
+- my $type = $cpu_module->getWSAAssignment('cpu_selection');
+- my $version = $cpu_module->getVersion();
+-
+- print "($index) $cpu - Class: $class Type: $type Version: $version\n";
++if( scalar(@cpulist) == 1 )
++{
++# Only one CPU to choose from...
++ $cpu_index = 1;
++}
++if (($cpu_index <= 0) || ($cpu_index > scalar(@cpulist))) {
++ print "\n--- Please select which CPU you wish to build the kernel against:\n\n";
++
++ my %cpuinfo;
++
++ $index = 1;
++ foreach my $cpu (@cpulist) {
++ my $cpu_module = $system->getCPU ($cpu);
++ if ($cpu_module->isEnabled ()) {
++ my $class = $cpu_module->getClass();
++ my $type = $cpu_module->getWSAAssignment('cpu_selection');
++ my $version = $cpu_module->getVersion();
++
++ print "($index) $cpu - Class: $class Type: $type Version: $version\n";
++ }
++ $index += 1;
+ }
+- $index += 1;
+-}
+
+-print "\n";
++ print "\n";
+
+-my $cpu_selection = $cpulist[request_answer (1, $index - 1) - 1];
++ $cpu_selection = $cpulist[request_answer (1, $index - 1) - 1];
++} else {
++ $cpu_selection = $cpulist[($cpu_index-1)];
++ print "Selected ($cpu_index) $cpu_selection as the main CPU";
++}
+
+ #
+ # Grab list of memory devices that $cpu_selection is hooked up to:
+@@ -109,6 +127,7 @@
+ #
+ # Select program memory to execute kernel from:
+ #
++
+ print "\n--- Please select a device to execute kernel from:\n\n";
+
+ $index = 1;
+@@ -119,7 +138,13 @@
+ }
+
+ my @memlist = keys (%meminfo);
+-my $mem_selected = $memlist[request_answer (1, $index - 1) - 1];
++if( scalar(@memlist) == 1)
++{
++ $mem_index = 1;
++} elsif (($mem_index <= 0) || ($mem_index > scalar(@memlist))) {
++ $mem_index = request_answer (1, $index -1);
++}
++$mem_selected = $memlist[$mem_index - 1];
+
+ print "\n--- Summary using\n\n";
+ print "PTF: $ptf_filename\n";
diff --git a/recipes/linux-libc-headers/linux-libc-headers-nios2-2.6.28/procinfo.h b/recipes/linux-libc-headers/linux-libc-headers-nios2-2.6.28/procinfo.h
new file mode 100644
index 0000000..8cdf828
--- /dev/null
+++ b/recipes/linux-libc-headers/linux-libc-headers-nios2-2.6.28/procinfo.h
@@ -0,0 +1,24 @@
+/*
+ * linux/include/asm-arm/procinfo.h
+ *
+ * Copyright (C) 1996-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_PROCINFO_H
+#define __ASM_PROCINFO_H
+
+#define HWCAP_SWP 1
+#define HWCAP_HALF 2
+#define HWCAP_THUMB 4
+#define HWCAP_26BIT 8 /* Play it safe */
+#define HWCAP_FAST_MULT 16
+#define HWCAP_FPA 32
+#define HWCAP_VFP 64
+#define HWCAP_EDSP 128
+#define HWCAP_JAVA 256
+#define HWCAP_IWMMXT 512
+#define HWCAP_CRUNCH 1024
+#endif
diff --git a/recipes/linux-libc-headers/linux-libc-headers-nios2-2.6.28/system.ptf b/recipes/linux-libc-headers/linux-libc-headers-nios2-2.6.28/system.ptf
new file mode 100755
index 0000000..8194067
--- /dev/null
+++ b/recipes/linux-libc-headers/linux-libc-headers-nios2-2.6.28/system.ptf
@@ -0,0 +1,3492 @@
+SYSTEM NIOS
+{
+ System_Wizard_Version = "9.00";
+ System_Wizard_Build = "132";
+ #
+ # Generated by: com.altera.sopcmodel.ensemble.EnsembleGeneratePTF
+ # Date: 2009.07.08.11:10:21
+ #
+ # clock_source "clk"
+ # altera_nios2 "cpu"
+ # altera_avalon_new_sdram_controller "ext_sdram"
+ # altera_avalon_timer "timer"
+ # altera_avalon_sysid "sysid"
+ # altera_avalon_tri_state_bridge "tristate_bridge"
+ # altera_avalon_cfi_flash "cfi_flash"
+ # clock_source "clk_half"
+ # altera_avalon_remote_update_cycloneiii "cycloneiii"
+ # altera_nios_custom_instr_floating_point "cpu_fpoint"
+ # fifoed_avalon_uart_classic "UART_backplane"
+ # fifoed_avalon_uart_classic "UART_daughter"
+ # fifoed_avalon_uart_classic "axonbus"
+ # opencores_i2c_master "I2C_local"
+ #
+ # Contains 31 connections.
+ #
+ Builder_Application = "sopc_builder_ca";
+ #. values for Builder_Application are:
+ #. sopc_builder_preview --> 6.1p, 7.0p prerelease versions
+ #. sopc_builder_ca --> 7.1 and later
+ #. (missing) --> 6.0 or earlier
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ hdl_language = "vhdl";
+ device_family = "CYCLONEIII";
+ device_family_id = "CYCLONEIII";
+ generate_sdk = "0";
+ do_build_sim = "0";
+ hardcopy_compatible = "0";
+ CLOCKS
+ {
+ CLOCK clk
+ {
+ frequency = "66660000";
+ source = "External";
+ Is_Clock_Source = "0";
+ display_name = "clk";
+ pipeline = "0";
+ clock_module_connection_point_for_c2h = "clk.clk";
+ }
+ CLOCK clk_half
+ {
+ frequency = "33330000";
+ source = "External";
+ Is_Clock_Source = "0";
+ display_name = "clk_half";
+ pipeline = "0";
+ clock_module_connection_point_for_c2h = "clk_half.clk";
+ }
+ }
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ clock_freq = "66660000";
+ board_class = "";
+ view_master_columns = "1";
+ view_master_priorities = "0";
+ generate_hdl = "";
+ bustype_column_width = "0";
+ clock_column_width = "80";
+ name_column_width = "75";
+ desc_column_width = "75";
+ base_column_width = "75";
+ end_column_width = "75";
+ BOARD_INFO
+ {
+ altera_avalon_cfi_flash
+ {
+ reference_designators = "";
+ }
+ }
+ }
+ MODULE cpu
+ {
+ MASTER instruction_master
+ {
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT i_address
+ {
+ type = "address";
+ width = "28";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT i_read
+ {
+ type = "read";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT i_readdata
+ {
+ type = "readdata";
+ width = "32";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT i_readdatavalid
+ {
+ type = "readdatavalid";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT i_waitrequest
+ {
+ type = "waitrequest";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Is_Asynchronous = "0";
+ DBS_Big_Endian = "0";
+ Adapts_To = "";
+ Do_Stream_Reads = "0";
+ Do_Stream_Writes = "0";
+ Max_Address_Width = "32";
+ Data_Width = "32";
+ Address_Width = "28";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "";
+ Linewrap_Bursts = "";
+ Burst_On_Burst_Boundaries_Only = "";
+ Always_Burst_Max_Burst = "";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ Is_Instruction_Master = "1";
+ Is_Readable = "1";
+ Is_Writeable = "0";
+ Address_Group = "0";
+ Has_IRQ = "0";
+ Irq_Scheme = "individual_requests";
+ Interrupt_Range = "0-0";
+ }
+ MEMORY_MAP
+ {
+ Entry cpu/jtag_debug_module
+ {
+ address = "0x08000800";
+ span = "0x00000800";
+ is_bridge = "0";
+ }
+ Entry ext_sdram/s1
+ {
+ address = "0x00000000";
+ span = "0x04000000";
+ is_bridge = "0";
+ }
+ Entry cfi_flash/s1
+ {
+ address = "0x04000000";
+ span = "0x02000000";
+ is_bridge = "0";
+ }
+ }
+ }
+ MASTER custom_instruction_master
+ {
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "nios_custom_instruction";
+ Data_Width = "32";
+ Address_Width = "8";
+ Is_Custom_Instruction = "1";
+ Is_Enabled = "1";
+ Max_Address_Width = "8";
+ Base_Address = "N/A";
+ Is_Visible = "0";
+ }
+ PORT_WIRING
+ {
+ PORT dataa
+ {
+ type = "dataa";
+ width = "32";
+ direction = "output";
+ }
+ PORT datab
+ {
+ type = "datab";
+ width = "32";
+ direction = "output";
+ }
+ PORT result
+ {
+ type = "result";
+ width = "32";
+ direction = "input";
+ }
+ PORT clk_en
+ {
+ type = "clk_en";
+ width = "1";
+ direction = "output";
+ }
+ PORT reset
+ {
+ type = "reset";
+ width = "1";
+ direction = "output";
+ }
+ PORT start
+ {
+ type = "start";
+ width = "1";
+ direction = "output";
+ }
+ PORT done
+ {
+ type = "done";
+ width = "1";
+ direction = "input";
+ }
+ PORT n
+ {
+ type = "n";
+ width = "8";
+ direction = "output";
+ }
+ PORT a
+ {
+ type = "a";
+ width = "5";
+ direction = "output";
+ }
+ PORT b
+ {
+ type = "b";
+ width = "5";
+ direction = "output";
+ }
+ PORT c
+ {
+ type = "c";
+ width = "5";
+ direction = "output";
+ }
+ PORT readra
+ {
+ type = "readra";
+ width = "1";
+ direction = "output";
+ }
+ PORT readrb
+ {
+ type = "readrb";
+ width = "1";
+ direction = "output";
+ }
+ PORT writerc
+ {
+ type = "writerc";
+ width = "1";
+ direction = "output";
+ }
+ }
+ }
+ SLAVE jtag_debug_module
+ {
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Write_Wait_States = "0cycles";
+ Read_Wait_States = "1cycles";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "dynamic";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Address_Span = "2048";
+ Read_Latency = "0";
+ Is_Memory_Device = "1";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "32";
+ Address_Width = "9";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ Accepts_External_Connections = "1";
+ Requires_Internal_Connections = "";
+ MASTERED_BY cpu/instruction_master
+ {
+ priority = "1";
+ Offset_Address = "0x08000800";
+ }
+ MASTERED_BY cpu/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x08000800";
+ }
+ Base_Address = "0x08000800";
+ Is_Readable = "1";
+ Is_Writeable = "1";
+ Uses_Tri_State_Data_Bus = "0";
+ Has_IRQ = "0";
+ JTAG_Hub_Base_Id = "1118278";
+ JTAG_Hub_Instance_Id = "0";
+ Address_Group = "0";
+ IRQ_MASTER cpu/data_master
+ {
+ IRQ_Number = "NC";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT jtag_debug_module_address
+ {
+ type = "address";
+ width = "9";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT jtag_debug_module_begintransfer
+ {
+ type = "begintransfer";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT jtag_debug_module_byteenable
+ {
+ type = "byteenable";
+ width = "4";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT jtag_debug_module_debugaccess
+ {
+ type = "debugaccess";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT jtag_debug_module_readdata
+ {
+ type = "readdata";
+ width = "32";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT jtag_debug_module_resetrequest
+ {
+ type = "resetrequest";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT jtag_debug_module_select
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT jtag_debug_module_write
+ {
+ type = "write";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT jtag_debug_module_writedata
+ {
+ type = "writedata";
+ width = "32";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ }
+ }
+ MASTER data_master
+ {
+ SYSTEM_BUILDER_INFO
+ {
+ Has_IRQ = "1";
+ Irq_Scheme = "individual_requests";
+ Bus_Type = "avalon";
+ Is_Asynchronous = "0";
+ DBS_Big_Endian = "0";
+ Adapts_To = "";
+ Do_Stream_Reads = "0";
+ Do_Stream_Writes = "0";
+ Max_Address_Width = "32";
+ Data_Width = "32";
+ Address_Width = "28";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ Is_Data_Master = "1";
+ Address_Group = "0";
+ Is_Readable = "1";
+ Is_Writeable = "1";
+ Interrupt_Range = "0-31";
+ }
+ PORT_WIRING
+ {
+ PORT d_irq
+ {
+ type = "irq";
+ width = "32";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT d_address
+ {
+ type = "address";
+ width = "28";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT d_byteenable
+ {
+ type = "byteenable";
+ width = "4";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT d_read
+ {
+ type = "read";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT d_readdata
+ {
+ type = "readdata";
+ width = "32";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT d_readdatavalid
+ {
+ type = "readdatavalid";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT d_waitrequest
+ {
+ type = "waitrequest";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT d_write
+ {
+ type = "write";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT d_writedata
+ {
+ type = "writedata";
+ width = "32";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT jtag_debug_module_debugaccess_to_roms
+ {
+ type = "debugaccess";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ }
+ MEMORY_MAP
+ {
+ Entry cpu/jtag_debug_module
+ {
+ address = "0x08000800";
+ span = "0x00000800";
+ is_bridge = "0";
+ }
+ Entry ext_sdram/s1
+ {
+ address = "0x00000000";
+ span = "0x04000000";
+ is_bridge = "0";
+ }
+ Entry timer/s1
+ {
+ address = "0x08000000";
+ span = "0x00000020";
+ is_bridge = "0";
+ }
+ Entry cfi_flash/s1
+ {
+ address = "0x04000000";
+ span = "0x02000000";
+ is_bridge = "0";
+ }
+ Entry sysid/control_slave
+ {
+ address = "0x07000020";
+ span = "0x00000008";
+ is_bridge = "0";
+ }
+ Entry cycloneiii/s1
+ {
+ address = "0x07010000";
+ span = "0x00000100";
+ is_bridge = "0";
+ }
+ Entry UART_backplane/s1
+ {
+ address = "0x07001160";
+ span = "0x00000020";
+ is_bridge = "0";
+ }
+ Entry UART_daughter/s1
+ {
+ address = "0x070011a0";
+ span = "0x00000020";
+ is_bridge = "0";
+ }
+ Entry axonbus/s1
+ {
+ address = "0x07001140";
+ span = "0x00000020";
+ is_bridge = "0";
+ }
+ Entry I2C_local/s1
+ {
+ address = "0x07001100";
+ span = "0x00000020";
+ is_bridge = "0";
+ }
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ cache_has_dcache = "1";
+ cache_dcache_size = "2048";
+ cache_dcache_line_size = "32";
+ cache_dcache_bursts = "0";
+ cache_dcache_ram_block_type = "AUTO";
+ num_tightly_coupled_data_masters = "0";
+ gui_num_tightly_coupled_data_masters = "0";
+ gui_include_tightly_coupled_data_masters = "0";
+ gui_omit_avalon_data_master = "0";
+ cache_has_icache = "1";
+ cache_icache_size = "4096";
+ cache_icache_line_size = "32";
+ cache_icache_ram_block_type = "AUTO";
+ cache_icache_bursts = "0";
+ num_tightly_coupled_instruction_masters = "0";
+ gui_num_tightly_coupled_instruction_masters = "0";
+ gui_include_tightly_coupled_instruction_masters = "0";
+ debug_level = "2";
+ include_oci = "1";
+ oci_num_xbrk = "0";
+ oci_num_dbrk = "0";
+ oci_dbrk_trace = "0";
+ oci_dbrk_pairs = "0";
+ oci_onchip_trace = "0";
+ oci_offchip_trace = "0";
+ oci_data_trace = "0";
+ include_third_party_debug_port = "0";
+ oci_trace_addr_width = "7";
+ oci_debugreq_signals = "0";
+ oci_trigger_arming = "1";
+ oci_embedded_pll = "0";
+ oci_assign_jtag_instance_id = "0";
+ oci_jtag_instance_id = "0";
+ oci_num_pm = "0";
+ oci_pm_width = "32";
+ performance_counters_present = "0";
+ performance_counters_width = "32";
+ always_encrypt = "1";
+ debug_simgen = "0";
+ activate_model_checker = "0";
+ activate_test_end_checker = "0";
+ activate_trace = "1";
+ activate_monitors = "1";
+ clear_x_bits_ld_non_bypass = "1";
+ bit_31_bypass_dcache = "1";
+ hdl_sim_caches_cleared = "1";
+ hbreak_test = "0";
+ allow_full_address_range = "0";
+ extra_exc_info = "0";
+ branch_prediction_type = "Dynamic";
+ bht_ptr_sz = "8";
+ bht_index_pc_only = "0";
+ gui_branch_prediction_type = "Automatic";
+ full_waveform_signals = "0";
+ export_pcb = "0";
+ avalon_debug_port_present = "0";
+ illegal_instructions_trap = "0";
+ illegal_memory_access_detection = "0";
+ illegal_mem_exc = "0";
+ slave_access_error_exc = "0";
+ division_error_exc = "0";
+ eic_present = "0";
+ num_shadow_reg_sets = "0";
+ gui_mmu_present = "0";
+ mmu_present = "0";
+ process_id_num_bits = "8";
+ tlb_ptr_sz = "7";
+ tlb_num_ways = "16";
+ udtlb_num_entries = "6";
+ uitlb_num_entries = "4";
+ fast_tlb_miss_exc_slave = "";
+ fast_tlb_miss_exc_offset = "0x00000000";
+ mpu_present = "0";
+ mpu_num_data_regions = "8";
+ mpu_num_inst_regions = "8";
+ mpu_min_data_region_size_log2 = "12";
+ mpu_min_inst_region_size_log2 = "12";
+ mpu_use_limit = "0";
+ hardware_divide_present = "0";
+ gui_hardware_divide_setting = "0";
+ hardware_multiply_present = "1";
+ hardware_multiply_impl = "embedded_mul";
+ shift_rot_impl = "fast_le_shift";
+ gui_hardware_multiply_setting = "embedded_mul_fast_le_shift";
+ reset_slave = "cfi_flash/s1";
+ break_slave = "cpu/jtag_debug_module";
+ exc_slave = "ext_sdram/s1";
+ reset_offset = "0x00400000";
+ break_offset = "0x00000020";
+ exc_offset = "0x00000020";
+ cpu_reset = "0";
+ CPU_Implementation = "fast";
+ cpu_selection = "f";
+ device_family_id = "CYCLONEIII";
+ address_stall_present = "1";
+ dsp_block_supports_shift = "0";
+ mrams_present = "0";
+ cpuid_value = "0";
+ dont_overwrite_cpuid = "1";
+ allow_legacy_sdk = "1";
+ legacy_sdk_support = "1";
+ inst_addr_width = "28";
+ data_addr_width = "28";
+ CPU_Architecture = "nios2";
+ cache_icache_burst_type = "none";
+ oci_sync_depth = "2";
+ hardware_multiply_omits_msw = "1";
+ big_endian = "0";
+ break_slave_override = "";
+ break_offset_override = "0x20";
+ altera_show_unreleased_features = "0";
+ altera_show_unpublished_features = "0";
+ altera_internal_test = "0";
+ alt_log_port_base = "";
+ alt_log_port_type = "";
+ cpuid_sz = "1";
+ gui_illegal_instructions_trap = "0";
+ advanced_exc = "0";
+ gui_illegal_memory_access_detection = "0";
+ cache_omit_dcache = "0";
+ cache_omit_icache = "0";
+ omit_instruction_master = "0";
+ omit_data_master = "0";
+ ras_ptr_sz = "4";
+ jtb_ptr_sz = "5";
+ ibuf_ptr_sz = "4";
+ always_bypass_dcache = "0";
+ iss_trace_on = "0";
+ iss_trace_warning = "1";
+ iss_trace_info = "1";
+ iss_trace_disassembly = "0";
+ iss_trace_registers = "0";
+ iss_trace_instr_count = "0";
+ iss_software_debug = "0";
+ iss_software_debug_port = "9996";
+ iss_memory_dump_start = "";
+ iss_memory_dump_end = "";
+ Boot_Copier = "boot_loader_cfi.srec";
+ Boot_Copier_EPCS = "boot_loader_epcs.srec";
+ Boot_Copier_EPCS_SII_SIII_CIII = "boot_loader_epcs_sii_siii_ciii.srec";
+ Boot_Copier_BE = "boot_loader_cfi_be.srec";
+ Boot_Copier_EPCS_BE = "boot_loader_epcs_be.srec";
+ Boot_Copier_EPCS_SII_SIII_CIII_BE = "boot_loader_epcs_sii_siii_ciii_be.srec";
+ CONSTANTS
+ {
+ CONSTANT __nios_catch_irqs__
+ {
+ value = "1";
+ comment = "Include panic handler for all irqs (needs uart)";
+ }
+ CONSTANT __nios_use_constructors__
+ {
+ value = "1";
+ comment = "Call c++ static constructors";
+ }
+ CONSTANT __nios_use_small_printf__
+ {
+ value = "1";
+ comment = "Smaller non-ANSI printf, with no floating point";
+ }
+ CONSTANT nasys_has_icache
+ {
+ value = "1";
+ comment = "True if instruction cache present";
+ }
+ CONSTANT nasys_icache_size
+ {
+ value = "4096";
+ comment = "Size in bytes of instruction cache";
+ }
+ CONSTANT nasys_icache_line_size
+ {
+ value = "32";
+ comment = "Size in bytes of each icache line";
+ }
+ CONSTANT nasys_icache_line_size_log2
+ {
+ value = "5";
+ comment = "Log2 size in bytes of each icache line";
+ }
+ CONSTANT nasys_has_dcache
+ {
+ value = "1";
+ comment = "True if instruction cache present";
+ }
+ CONSTANT nasys_dcache_size
+ {
+ value = "2048";
+ comment = "Size in bytes of data cache";
+ }
+ CONSTANT nasys_dcache_line_size
+ {
+ value = "32";
+ comment = "Size in bytes of each dcache line";
+ }
+ CONSTANT nasys_dcache_line_size_log2
+ {
+ value = "5";
+ comment = "Log2 size in bytes of each dcache line";
+ }
+ }
+ license_status = "";
+ mainmem_slave = "cfi_flash/s1";
+ datamem_slave = "cfi_flash/s1";
+ maincomm_slave = "axonbus/s1";
+ germs_monitor_id = "";
+ }
+ class = "altera_nios2";
+ class_version = "7.080900";
+ SYSTEM_BUILDER_INFO
+ {
+ Is_Enabled = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ Parameters_Signature = "";
+ Is_CPU = "1";
+ Instantiate_In_System_Module = "1";
+ Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,STRATIXIIGXLITE,STRATIXIII,STRATIXIV,CYCLONE,CYCLONEII,CYCLONEIII,HARDCOPYIII,ARRIAII,TARPON,HARDCOPYIV";
+ Default_Module_Name = "cpu";
+ Top_Level_Ports_Are_Enumerated = "1";
+ View
+ {
+ Settings_Summary = "Nios II/f
+ <br> 4-Kbyte Instruction Cache
+ <br> 2-Kbyte Data Cache
+ <br> JTAG Debug Module
+ ";
+ MESSAGES
+ {
+ }
+ }
+ }
+ iss_model_name = "altera_nios2";
+ HDL_INFO
+ {
+ # The list of files associated with this module (for synthesis
+ # and other purposes) depends on the users' wizard-choices.
+ # This section will be filled-in by the Generator_Program
+ # after the module logic has been created and the
+ # various filenames are known.
+ }
+ MASTER tightly_coupled_instruction_master_0
+ {
+ PORT_WIRING
+ {
+ # The number and kind of ports that appear on this module
+ # depends on the user's wizard-choices.
+ # This section will be filled-in by the Generator_Program after
+ # the module logic has been created and the ports are known.
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Register_Incoming_Signals = "0";
+ Bus_Type = "avalon";
+ Data_Width = "32";
+ Max_Address_Width = "31";
+ Address_Width = "8";
+ Is_Instruction_Master = "1";
+ Has_IRQ = "0";
+ Is_Enabled = "0";
+ Is_Big_Endian = "0";
+ Connection_Limit = "1";
+ Is_Channel = "1";
+ }
+ }
+ MASTER tightly_coupled_instruction_master_1
+ {
+ PORT_WIRING
+ {
+ # The number and kind of ports that appear on this module
+ # depends on the user's wizard-choices.
+ # This section will be filled-in by the Generator_Program after
+ # the module logic has been created and the ports are known.
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Register_Incoming_Signals = "0";
+ Bus_Type = "avalon";
+ Data_Width = "32";
+ Max_Address_Width = "31";
+ Address_Width = "8";
+ Address_Group = "0";
+ Is_Instruction_Master = "1";
+ Is_Readable = "1";
+ Is_Writeable = "0";
+ Has_IRQ = "0";
+ Is_Enabled = "0";
+ Is_Big_Endian = "0";
+ Connection_Limit = "1";
+ Is_Channel = "1";
+ }
+ }
+ MASTER tightly_coupled_instruction_master_2
+ {
+ PORT_WIRING
+ {
+ # The number and kind of ports that appear on this module
+ # depends on the user's wizard-choices.
+ # This section will be filled-in by the Generator_Program after
+ # the module logic has been created and the ports are known.
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Register_Incoming_Signals = "0";
+ Bus_Type = "avalon";
+ Data_Width = "32";
+ Max_Address_Width = "31";
+ Address_Width = "8";
+ Address_Group = "0";
+ Is_Instruction_Master = "1";
+ Is_Readable = "1";
+ Is_Writeable = "0";
+ Has_IRQ = "0";
+ Is_Enabled = "0";
+ Is_Big_Endian = "0";
+ Connection_Limit = "1";
+ Is_Channel = "1";
+ }
+ }
+ MASTER tightly_coupled_instruction_master_3
+ {
+ PORT_WIRING
+ {
+ # The number and kind of ports that appear on this module
+ # depends on the user's wizard-choices.
+ # This section will be filled-in by the Generator_Program after
+ # the module logic has been created and the ports are known.
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Register_Incoming_Signals = "0";
+ Bus_Type = "avalon";
+ Data_Width = "32";
+ Max_Address_Width = "31";
+ Address_Width = "8";
+ Address_Group = "0";
+ Is_Instruction_Master = "1";
+ Is_Readable = "1";
+ Is_Writeable = "0";
+ Has_IRQ = "0";
+ Is_Enabled = "0";
+ Is_Big_Endian = "0";
+ Connection_Limit = "1";
+ Is_Channel = "1";
+ }
+ }
+ MASTER data_master2
+ {
+ PORT_WIRING
+ {
+ # The number and kind of ports that appear on this module
+ # depends on the user's wizard-choices.
+ # This section will be filled-in by the Generator_Program after
+ # the module logic has been created and the ports are known.
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Register_Incoming_Signals = "1";
+ Bus_Type = "avalon";
+ Data_Width = "32";
+ Max_Address_Width = "31";
+ Address_Width = "8";
+ Address_Group = "0";
+ Is_Data_Master = "1";
+ Is_Readable = "1";
+ Is_Writeable = "1";
+ Has_IRQ = "0";
+ Is_Enabled = "0";
+ Is_Big_Endian = "0";
+ }
+ }
+ MASTER tightly_coupled_data_master_0
+ {
+ PORT_WIRING
+ {
+ # The number and kind of ports that appear on this module
+ # depends on the user's wizard-choices.
+ # This section will be filled-in by the Generator_Program after
+ # the module logic has been created and the ports are known.
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Register_Incoming_Signals = "0";
+ Bus_Type = "avalon";
+ Data_Width = "32";
+ Max_Address_Width = "31";
+ Address_Width = "8";
+ Address_Group = "0";
+ Is_Data_Master = "1";
+ Is_Readable = "1";
+ Is_Writeable = "1";
+ Has_IRQ = "0";
+ Is_Enabled = "0";
+ Is_Big_Endian = "0";
+ Connection_Limit = "1";
+ Is_Channel = "1";
+ }
+ }
+ MASTER tightly_coupled_data_master_1
+ {
+ PORT_WIRING
+ {
+ # The number and kind of ports that appear on this module
+ # depends on the user's wizard-choices.
+ # This section will be filled-in by the Generator_Program after
+ # the module logic has been created and the ports are known.
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Register_Incoming_Signals = "0";
+ Bus_Type = "avalon";
+ Data_Width = "32";
+ Max_Address_Width = "31";
+ Address_Width = "8";
+ Address_Group = "0";
+ Is_Data_Master = "1";
+ Is_Readable = "1";
+ Is_Writeable = "1";
+ Has_IRQ = "0";
+ Is_Enabled = "0";
+ Is_Big_Endian = "0";
+ Connection_Limit = "1";
+ Is_Channel = "1";
+ }
+ }
+ MASTER tightly_coupled_data_master_2
+ {
+ PORT_WIRING
+ {
+ # The number and kind of ports that appear on this module
+ # depends on the user's wizard-choices.
+ # This section will be filled-in by the Generator_Program after
+ # the module logic has been created and the ports are known.
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Register_Incoming_Signals = "0";
+ Bus_Type = "avalon";
+ Data_Width = "32";
+ Max_Address_Width = "31";
+ Address_Width = "8";
+ Address_Group = "0";
+ Is_Data_Master = "1";
+ Is_Readable = "1";
+ Is_Writeable = "1";
+ Has_IRQ = "0";
+ Is_Enabled = "0";
+ Is_Big_Endian = "0";
+ Connection_Limit = "1";
+ Is_Channel = "1";
+ }
+ }
+ MASTER tightly_coupled_data_master_3
+ {
+ PORT_WIRING
+ {
+ # The number and kind of ports that appear on this module
+ # depends on the user's wizard-choices.
+ # This section will be filled-in by the Generator_Program after
+ # the module logic has been created and the ports are known.
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Register_Incoming_Signals = "0";
+ Bus_Type = "avalon";
+ Data_Width = "32";
+ Max_Address_Width = "31";
+ Address_Width = "8";
+ Address_Group = "0";
+ Is_Data_Master = "1";
+ Is_Readable = "1";
+ Is_Writeable = "1";
+ Has_IRQ = "0";
+ Is_Enabled = "0";
+ Is_Big_Endian = "0";
+ Connection_Limit = "1";
+ Is_Channel = "1";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT jtag_debug_trigout
+ {
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT jtag_debug_offchip_trace_clk
+ {
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT jtag_debug_offchip_trace_data
+ {
+ width = "18";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT clkx2
+ {
+ width = "1";
+ direction = "input";
+ Is_Enabled = "0";
+ visible = "0";
+ }
+ }
+ }
+ MODULE ext_sdram
+ {
+ SLAVE s1
+ {
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT az_addr
+ {
+ type = "address";
+ width = "24";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT az_be_n
+ {
+ type = "byteenable_n";
+ width = "4";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT az_cs
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT az_data
+ {
+ type = "writedata";
+ width = "32";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT az_rd_n
+ {
+ type = "read_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT az_wr_n
+ {
+ type = "write_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT za_data
+ {
+ type = "readdata";
+ width = "32";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT za_valid
+ {
+ type = "readdatavalid";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT za_waitrequest
+ {
+ type = "waitrequest";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT zs_addr
+ {
+ direction = "output";
+ width = "13";
+ Is_Enabled = "0";
+ }
+ PORT zs_ba
+ {
+ direction = "output";
+ width = "2";
+ Is_Enabled = "0";
+ }
+ PORT zs_cas_n
+ {
+ direction = "output";
+ width = "1";
+ Is_Enabled = "0";
+ }
+ PORT zs_cke
+ {
+ direction = "output";
+ width = "1";
+ Is_Enabled = "0";
+ }
+ PORT zs_cs_n
+ {
+ direction = "output";
+ width = "1";
+ Is_Enabled = "0";
+ }
+ PORT zs_dq
+ {
+ direction = "inout";
+ width = "32";
+ Is_Enabled = "0";
+ }
+ PORT zs_dqm
+ {
+ direction = "output";
+ width = "4";
+ Is_Enabled = "0";
+ }
+ PORT zs_ras_n
+ {
+ direction = "output";
+ width = "1";
+ Is_Enabled = "0";
+ }
+ PORT zs_we_n
+ {
+ direction = "output";
+ width = "1";
+ Is_Enabled = "0";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Read_Wait_States = "peripheral_controlled";
+ Write_Wait_States = "peripheral_controlled";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "dynamic";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Address_Span = "67108864";
+ Read_Latency = "0";
+ Is_Memory_Device = "1";
+ Maximum_Pending_Read_Transactions = "9";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "32";
+ Address_Width = "24";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu/instruction_master
+ {
+ priority = "1";
+ Offset_Address = "0x00000000";
+ }
+ MASTERED_BY cpu/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x00000000";
+ }
+ Base_Address = "0x00000000";
+ Has_IRQ = "0";
+ Simulation_Num_Lanes = "1";
+ Address_Group = "0";
+ IRQ_MASTER cpu/data_master
+ {
+ IRQ_Number = "NC";
+ }
+ }
+ }
+ iss_model_name = "altera_memory";
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ register_data_in = "1";
+ sim_model_base = "0";
+ sdram_data_width = "32";
+ sdram_addr_width = "13";
+ sdram_row_width = "13";
+ sdram_col_width = "9";
+ sdram_num_chipselects = "1";
+ sdram_num_banks = "4";
+ refresh_period = "15.625";
+ powerup_delay = "200.0";
+ cas_latency = "3";
+ t_rfc = "70.0";
+ t_rp = "20.0";
+ t_mrd = "3";
+ t_rcd = "20.0";
+ t_ac = "5.5";
+ t_wr = "14.0";
+ init_refresh_commands = "2";
+ init_nop_delay = "0.0";
+ shared_data = "1";
+ sdram_bank_width = "2";
+ tristate_bridge_slave = "tristate_bridge/avalon_slave";
+ starvation_indicator = "0";
+ is_initialized = "1";
+ }
+ SIMULATION
+ {
+ DISPLAY
+ {
+ SIGNAL a
+ {
+ name = "az_addr";
+ radix = "hexadecimal";
+ }
+ SIGNAL b
+ {
+ name = "az_be_n";
+ radix = "hexadecimal";
+ }
+ SIGNAL c
+ {
+ name = "az_cs";
+ }
+ SIGNAL d
+ {
+ name = "az_data";
+ radix = "hexadecimal";
+ }
+ SIGNAL e
+ {
+ name = "az_rd_n";
+ }
+ SIGNAL f
+ {
+ name = "az_wr_n";
+ }
+ SIGNAL h
+ {
+ name = "za_data";
+ radix = "hexadecimal";
+ }
+ SIGNAL i
+ {
+ name = "za_valid";
+ }
+ SIGNAL j
+ {
+ name = "za_waitrequest";
+ }
+ SIGNAL l
+ {
+ name = "CODE";
+ radix = "ascii";
+ }
+ SIGNAL g
+ {
+ name = "clk";
+ }
+ SIGNAL k
+ {
+ name = "za_cannotrefresh";
+ suppress = "1";
+ }
+ SIGNAL m
+ {
+ name = "zs_addr";
+ radix = "hexadecimal";
+ suppress = "1";
+ }
+ SIGNAL n
+ {
+ name = "zs_ba";
+ radix = "hexadecimal";
+ suppress = "1";
+ }
+ SIGNAL o
+ {
+ name = "zs_cs_n";
+ radix = "hexadecimal";
+ suppress = "1";
+ }
+ SIGNAL p
+ {
+ name = "zs_ras_n";
+ suppress = "1";
+ }
+ SIGNAL q
+ {
+ name = "zs_cas_n";
+ suppress = "1";
+ }
+ SIGNAL r
+ {
+ name = "zs_we_n";
+ suppress = "1";
+ }
+ SIGNAL s
+ {
+ name = "zs_dq";
+ radix = "hexadecimal";
+ suppress = "1";
+ }
+ SIGNAL t
+ {
+ name = "zs_dqm";
+ radix = "hexadecimal";
+ suppress = "1";
+ }
+ SIGNAL u
+ {
+ name = "zt_addr";
+ radix = "hexadecimal";
+ suppress = "0";
+ }
+ SIGNAL v
+ {
+ name = "zt_ba";
+ radix = "hexadecimal";
+ suppress = "0";
+ }
+ SIGNAL w
+ {
+ name = "zt_oe";
+ suppress = "0";
+ }
+ SIGNAL x
+ {
+ name = "zt_cke";
+ suppress = "0";
+ }
+ SIGNAL y
+ {
+ name = "zt_chipselect";
+ suppress = "0";
+ }
+ SIGNAL z0
+ {
+ name = "zt_lock_n";
+ suppress = "0";
+ }
+ SIGNAL z1
+ {
+ name = "zt_ras_n";
+ suppress = "0";
+ }
+ SIGNAL z2
+ {
+ name = "zt_cas_n";
+ suppress = "0";
+ }
+ SIGNAL z3
+ {
+ name = "zt_we_n";
+ suppress = "0";
+ }
+ SIGNAL z4
+ {
+ name = "zt_cs_n";
+ radix = "hexadecimal";
+ suppress = "0";
+ }
+ SIGNAL z5
+ {
+ name = "zt_dqm";
+ radix = "hexadecimal";
+ suppress = "0";
+ }
+ SIGNAL z6
+ {
+ name = "zt_data";
+ radix = "hexadecimal";
+ suppress = "0";
+ }
+ SIGNAL z7
+ {
+ name = "tz_data";
+ radix = "hexadecimal";
+ suppress = "0";
+ }
+ SIGNAL z8
+ {
+ name = "tz_waitrequest";
+ suppress = "0";
+ }
+ }
+ Fix_Me_Up = "";
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Instantiate_In_System_Module = "1";
+ Is_Enabled = "1";
+ Default_Module_Name = "sdram";
+ Top_Level_Ports_Are_Enumerated = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ Disable_Simulation_Port_Wiring = "1";
+ View
+ {
+ MESSAGES
+ {
+ }
+ Settings_Summary = "16777216 x 32<br>
+ Memory size: 64 MBytes<br>
+ 512 MBits
+ <br>Sharing Pins Via Tristate Bridge";
+ }
+ }
+ class = "altera_avalon_new_sdram_controller";
+ class_version = "7.080900";
+ }
+ MODULE timer
+ {
+ SLAVE s1
+ {
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT irq
+ {
+ type = "irq";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT address
+ {
+ type = "address";
+ width = "3";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT writedata
+ {
+ type = "writedata";
+ width = "16";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT readdata
+ {
+ type = "readdata";
+ width = "16";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT chipselect
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT write_n
+ {
+ type = "write_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Has_IRQ = "1";
+ Bus_Type = "avalon";
+ Write_Wait_States = "0cycles";
+ Read_Wait_States = "1cycles";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "native";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Read_Latency = "0";
+ Is_Memory_Device = "0";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "16";
+ Address_Width = "3";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x08000000";
+ }
+ IRQ_MASTER cpu/data_master
+ {
+ IRQ_Number = "6";
+ }
+ Base_Address = "0x08000000";
+ Address_Group = "0";
+ }
+ }
+ class = "altera_avalon_timer";
+ class_version = "7.080900";
+ iss_model_name = "altera_avalon_timer";
+ SYSTEM_BUILDER_INFO
+ {
+ Instantiate_In_System_Module = "1";
+ Is_Enabled = "1";
+ Top_Level_Ports_Are_Enumerated = "1";
+ View
+ {
+ Settings_Summary = "Timer with 1 ms timeout period.";
+ Is_Collapsed = "1";
+ MESSAGES
+ {
+ }
+ }
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ always_run = "0";
+ fixed_period = "0";
+ snapshot = "1";
+ period = "1";
+ period_units = "ms";
+ reset_output = "0";
+ timeout_pulse_output = "0";
+ load_value = "66659";
+ counter_size = "32";
+ mult = "0.0010";
+ ticks_per_sec = "1000";
+ }
+ }
+ MODULE sysid
+ {
+ SLAVE control_slave
+ {
+ PORT_WIRING
+ {
+ PORT clock
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT address
+ {
+ type = "address";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT readdata
+ {
+ type = "readdata";
+ width = "32";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Write_Wait_States = "0cycles";
+ Read_Wait_States = "1cycles";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "native";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Read_Latency = "0";
+ Is_Memory_Device = "0";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "32";
+ Address_Width = "1";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x07000020";
+ }
+ Base_Address = "0x07000020";
+ Has_IRQ = "0";
+ Address_Group = "0";
+ IRQ_MASTER cpu/data_master
+ {
+ IRQ_Number = "NC";
+ }
+ }
+ }
+ class = "altera_avalon_sysid";
+ class_version = "7.080900";
+ SYSTEM_BUILDER_INFO
+ {
+ Date_Modified = "";
+ Is_Enabled = "1";
+ Instantiate_In_System_Module = "1";
+ Fixed_Module_Name = "sysid";
+ Top_Level_Ports_Are_Enumerated = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ View
+ {
+ Settings_Summary = "No system ID yet. <br>
+ A unique ID is assigned every time <br>
+ the system is generated.";
+ MESSAGES
+ {
+ }
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ id = "1371320681";
+ timestamp = "1247051407";
+ regenerate_values = "0";
+ }
+ HDL_INFO
+ {
+ # The list of files associated with this module (for synthesis
+ # and other purposes) depends on the users' wizard-choices.
+ # This section will be filled-in by the Generator_Program
+ # after the module logic has been created and the
+ # various filenames are known.
+ }
+ PORT_WIRING
+ {
+ # The number and kind of ports that appear on this module
+ # depends on the user's wizard-choices.
+ # This section will be filled-in by the Generator_Program
+ # after the module logic has been created and the ports are known.
+ #
+ }
+ }
+ MODULE tristate_bridge
+ {
+ SLAVE avalon_slave
+ {
+ PORT_WIRING
+ {
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Write_Wait_States = "0cycles";
+ Read_Wait_States = "1cycles";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "dynamic";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Address_Span = "1";
+ Read_Latency = "0";
+ Is_Memory_Device = "0";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "1";
+ Register_Outgoing_Signals = "1";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu/instruction_master
+ {
+ priority = "1";
+ Offset_Address = "N/A";
+ Base_Address = "N/A";
+ }
+ MASTERED_BY cpu/data_master
+ {
+ priority = "1";
+ Offset_Address = "N/A";
+ Base_Address = "N/A";
+ }
+ Bridges_To = "tristate_master";
+ Base_Address = "N/A";
+ Has_IRQ = "0";
+ IRQ = "N/A";
+ Address_Group = "0";
+ IRQ_MASTER cpu/data_master
+ {
+ IRQ_Number = "NC";
+ }
+ }
+ }
+ MASTER tristate_master
+ {
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon_tristate";
+ Is_Asynchronous = "0";
+ DBS_Big_Endian = "0";
+ Adapts_To = "";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ Bridges_To = "avalon_slave";
+ }
+ PORT_WIRING
+ {
+ }
+ MEMORY_MAP
+ {
+ Entry cfi_flash/s1
+ {
+ address = "0x04000000";
+ span = "0x02000000";
+ is_bridge = "0";
+ }
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ }
+ class = "altera_avalon_tri_state_bridge";
+ class_version = "7.080900";
+ SYSTEM_BUILDER_INFO
+ {
+ Is_Enabled = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ Instantiate_In_System_Module = "1";
+ Is_Bridge = "1";
+ Top_Level_Ports_Are_Enumerated = "1";
+ View
+ {
+ MESSAGES
+ {
+ }
+ }
+ }
+ }
+ MODULE cfi_flash
+ {
+ SLAVE s1
+ {
+ PORT_WIRING
+ {
+ PORT data
+ {
+ type = "data";
+ width = "16";
+ direction = "inout";
+ Is_Enabled = "1";
+ is_shared = "1";
+ }
+ PORT address
+ {
+ type = "address";
+ width = "24";
+ direction = "input";
+ Is_Enabled = "1";
+ is_shared = "1";
+ }
+ PORT read_n
+ {
+ type = "read_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ is_shared = "0";
+ }
+ PORT write_n
+ {
+ type = "write_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ is_shared = "0";
+ }
+ PORT select_n
+ {
+ type = "chipselect_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ is_shared = "0";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon_tristate";
+ Write_Wait_States = "100ns";
+ Read_Wait_States = "100ns";
+ Hold_Time = "20ns";
+ Setup_Time = "25ns";
+ Is_Printable_Device = "0";
+ Address_Alignment = "dynamic";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "1";
+ Address_Span = "33554432";
+ Read_Latency = "0";
+ Is_Memory_Device = "1";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "1";
+ Active_CS_Through_Read_Latency = "0";
+ Data_Width = "16";
+ Address_Width = "24";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY tristate_bridge/tristate_master
+ {
+ priority = "1";
+ Offset_Address = "0x04000000";
+ }
+ Base_Address = "0x04000000";
+ Has_IRQ = "0";
+ Simulation_Num_Lanes = "1";
+ Convert_Xs_To_0 = "1";
+ Address_Group = "0";
+ IRQ_MASTER cpu/data_master
+ {
+ IRQ_Number = "NC";
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ class = "altera_avalon_cfi_flash";
+ Supports_Flash_File_System = "1";
+ flash_reference_designator = "";
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ Setup_Value = "25";
+ Wait_Value = "100";
+ Hold_Value = "20";
+ Timing_Units = "ns";
+ Unit_Multiplier = "1";
+ Size = "33554432";
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Simulation_Num_Lanes = "2";
+ Is_Enabled = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ Make_Memory_Model = "1";
+ Instantiate_In_System_Module = "0";
+ Top_Level_Ports_Are_Enumerated = "1";
+ View
+ {
+ MESSAGES
+ {
+ }
+ }
+ }
+ class = "altera_avalon_cfi_flash";
+ class_version = "7.080900";
+ iss_model_name = "altera_avalon_flash";
+ HDL_INFO
+ {
+ }
+ }
+ MODULE cycloneiii
+ {
+ SLAVE s1
+ {
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset
+ {
+ type = "reset";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT writedata
+ {
+ type = "writedata";
+ width = "32";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT readdata
+ {
+ type = "readdata";
+ width = "32";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT address
+ {
+ type = "address";
+ width = "6";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT chipselect
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT write
+ {
+ type = "write";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT read
+ {
+ type = "read";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT waitrequest
+ {
+ type = "waitrequest";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Read_Wait_States = "peripheral_controlled";
+ Write_Wait_States = "peripheral_controlled";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "native";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Read_Latency = "2";
+ Is_Memory_Device = "0";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "32";
+ Address_Width = "6";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x07010000";
+ ADAPTER_MASTER NIOS_clock_0/out
+ {
+ priority = "1";
+ }
+ }
+ Base_Address = "0x07010000";
+ Address_Group = "0";
+ IRQ_MASTER cpu/data_master
+ {
+ IRQ_Number = "NC";
+ }
+ }
+ }
+ class = "no_legacy_module";
+ class_version = "7.080900";
+ gtf_class_name = "altera_avalon_remote_update_cycloneiii";
+ gtf_class_version = "9.0";
+ SYSTEM_BUILDER_INFO
+ {
+ Do_Not_Generate = "1";
+ Instantiate_In_System_Module = "1";
+ Is_Bridge = "0";
+ Is_Enabled = "1";
+ Clock_Source = "clk_half";
+ Has_Clock = "1";
+ View
+ {
+ MESSAGES
+ {
+ }
+ }
+ }
+ HDL_INFO
+ {
+ Simulation_HDL_Files = "/home/walter/VHDL/SYGEG1-080630/VHDL/Quartus_Altera/Prj/cycloneiii.vho";
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ terminated_ports
+ {
+ }
+ }
+ }
+ MODULE cpu_fpoint
+ {
+ SLAVE s1
+ {
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "nios_custom_instruction";
+ Data_Width = "32";
+ Address_Width = "2";
+ Is_Custom_Instruction = "1";
+ Is_Enabled = "1";
+ ci_operands = "2";
+ ci_cycles = "1";
+ ci_inst_type = "variable multicycle";
+ Has_Base_Address = "1";
+ Base_Address = "0x000000fc";
+ ci_macro_name = "fpoint";
+ MASTERED_BY cpu/custom_instruction_master
+ {
+ priority = "1";
+ }
+ IRQ_MASTER cpu/custom_instruction_master
+ {
+ IRQ_Number = "NC";
+ }
+ Is_Base_Locked = "1";
+ Is_Visible = "0";
+ Address_Group = "0";
+ }
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ }
+ PORT clk_en
+ {
+ type = "clk_en";
+ width = "1";
+ direction = "input";
+ }
+ PORT reset
+ {
+ type = "reset";
+ width = "1";
+ direction = "input";
+ }
+ PORT start
+ {
+ type = "start";
+ width = "1";
+ direction = "input";
+ }
+ PORT n
+ {
+ type = "n";
+ width = "2";
+ direction = "input";
+ }
+ PORT dataa
+ {
+ type = "dataa";
+ width = "32";
+ direction = "input";
+ }
+ PORT datab
+ {
+ type = "datab";
+ width = "32";
+ direction = "input";
+ }
+ PORT result
+ {
+ type = "result";
+ width = "32";
+ direction = "output";
+ }
+ PORT done
+ {
+ type = "done";
+ width = "1";
+ direction = "output";
+ }
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ Use_Divider = "0";
+ ci_macro_name = "fpoint";
+ ci_cycles = "1";
+ ci_instr_format = "RR";
+ ci_has_prefix = "0";
+ ci_inst_type = "variable multicycle";
+ ci_operands = "2";
+ Precision = "1";
+ Reduced_Operation = "0";
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Is_Custom_Instruction = "1";
+ Is_Enabled = "1";
+ Date_Modified = "";
+ Is_Visible = "0";
+ Instantiate_In_System_Module = "1";
+ Clock_Source = "clk";
+ View
+ {
+ MESSAGES
+ {
+ }
+ }
+ }
+ SIMULATION
+ {
+ DISPLAY
+ {
+ SIGNAL a
+ {
+ name = "clk";
+ }
+ SIGNAL b
+ {
+ name = "clk_en";
+ }
+ SIGNAL c
+ {
+ name = "reset";
+ }
+ SIGNAL d
+ {
+ name = "start";
+ }
+ SIGNAL e
+ {
+ name = "n";
+ radix = "hexadecimal";
+ }
+ SIGNAL f
+ {
+ name = "dataa";
+ radix = "hexadecimal";
+ }
+ SIGNAL g
+ {
+ name = "datab";
+ radix = "hexadecimal";
+ }
+ SIGNAL h
+ {
+ name = "result";
+ radix = "hexadecimal";
+ }
+ SIGNAL i
+ {
+ name = "done";
+ }
+ }
+ }
+ class = "altera_nios_custom_instr_floating_point";
+ class_version = "7.080900";
+ }
+ MODULE UART_backplane
+ {
+ SLAVE s1
+ {
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT irq
+ {
+ type = "irq";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT address
+ {
+ type = "address";
+ width = "3";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT begintransfer
+ {
+ type = "begintransfer";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT chipselect
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT read_n
+ {
+ type = "read_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT write_n
+ {
+ type = "write_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT writedata
+ {
+ type = "writedata";
+ width = "16";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT dataavailable
+ {
+ type = "dataavailable";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT readdata
+ {
+ type = "readdata";
+ width = "16";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT readyfordata
+ {
+ type = "readyfordata";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Has_IRQ = "1";
+ Bus_Type = "avalon";
+ Write_Wait_States = "1cycles";
+ Read_Wait_States = "1cycles";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "1";
+ Address_Alignment = "native";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Read_Latency = "0";
+ Is_Memory_Device = "0";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "16";
+ Address_Width = "3";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x07001160";
+ }
+ IRQ_MASTER cpu/data_master
+ {
+ IRQ_Number = "4";
+ }
+ Base_Address = "0x07001160";
+ Address_Group = "0";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT txd
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT rxd
+ {
+ type = "export";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT rxused
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT txused
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT transmitting
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT cts_n
+ {
+ type = "export";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "0";
+ }
+ PORT rts_n
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT irqexport
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ }
+ class = "fifoed_avalon_uart";
+ class_version = "7.1";
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ use_tx_fifo = "1";
+ use_rx_fifo = "1";
+ baud = "115200";
+ data_bits = "8";
+ fixed_baud = "1";
+ parity = "N";
+ stop_bits = "1";
+ use_cts_rts = "0";
+ use_eop_register = "0";
+ sim_true_baud = "0";
+ sim_char_stream = "";
+ use_fifo = "0";
+ fifo_size = "16";
+ fifo_export_used = "0";
+ export_irq = "0";
+ hw_cts = "0";
+ trans_pin = "0";
+ fifo_size_tx = "8";
+ fifo_size_rx = "8";
+ tx_fifo_LE = "0";
+ rx_fifo_LE = "0";
+ combine_fifo = "0";
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Is_Enabled = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ Instantiate_In_System_Module = "1";
+ View
+ {
+ MESSAGES
+ {
+ }
+ Settings_Summary = "8-bit UART with 115200 baud, <br>
+ 1 stop bits and N parity";
+ }
+ }
+ SIMULATION
+ {
+ DISPLAY
+ {
+ SIGNAL a
+ {
+ name = " Bus Interface";
+ format = "Divider";
+ }
+ SIGNAL b
+ {
+ name = "chipselect";
+ }
+ SIGNAL c
+ {
+ name = "address";
+ radix = "hexadecimal";
+ }
+ SIGNAL d
+ {
+ name = "writedata";
+ radix = "hexadecimal";
+ }
+ SIGNAL e
+ {
+ name = "readdata";
+ radix = "hexadecimal";
+ }
+ SIGNAL f
+ {
+ name = " Internals";
+ format = "Divider";
+ }
+ SIGNAL g
+ {
+ name = "tx_ready";
+ }
+ SIGNAL h
+ {
+ name = "tx_data";
+ radix = "ascii";
+ }
+ SIGNAL i
+ {
+ name = "rx_char_ready";
+ }
+ SIGNAL j
+ {
+ name = "rx_data";
+ radix = "ascii";
+ }
+ }
+ INTERACTIVE_OUT log
+ {
+ enable = "0";
+ file = "_log_module.txt";
+ # suffix to $module_name in em_uart.pl
+ radix = "ascii";
+ signals = "temp,list";
+ exe = "perl -- tail-f.pl";
+ }
+ INTERACTIVE_IN drive
+ {
+ enable = "0";
+ # file descriptors are really just suffixes used by perl...
+ file = "_input_data_stream.dat";
+ mutex = "_input_data_mutex.dat";
+ log = "_in.log";
+ rate = "100";
+ signals = "temp,list";
+ exe = "perl -- uart.pl";
+ }
+ }
+ }
+ MODULE UART_daughter
+ {
+ SLAVE s1
+ {
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT irq
+ {
+ type = "irq";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT address
+ {
+ type = "address";
+ width = "3";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT begintransfer
+ {
+ type = "begintransfer";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT chipselect
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT read_n
+ {
+ type = "read_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT write_n
+ {
+ type = "write_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT writedata
+ {
+ type = "writedata";
+ width = "16";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT dataavailable
+ {
+ type = "dataavailable";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT readdata
+ {
+ type = "readdata";
+ width = "16";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT readyfordata
+ {
+ type = "readyfordata";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Has_IRQ = "1";
+ Bus_Type = "avalon";
+ Write_Wait_States = "1cycles";
+ Read_Wait_States = "1cycles";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "1";
+ Address_Alignment = "native";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Read_Latency = "0";
+ Is_Memory_Device = "0";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "16";
+ Address_Width = "3";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x070011a0";
+ }
+ IRQ_MASTER cpu/data_master
+ {
+ IRQ_Number = "5";
+ }
+ Base_Address = "0x070011a0";
+ Address_Group = "0";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT txd
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT rxd
+ {
+ type = "export";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT rxused
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT txused
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT transmitting
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT cts_n
+ {
+ type = "export";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "0";
+ }
+ PORT rts_n
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT irqexport
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ }
+ class = "fifoed_avalon_uart";
+ class_version = "7.1";
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ use_tx_fifo = "1";
+ use_rx_fifo = "1";
+ baud = "115200";
+ data_bits = "8";
+ fixed_baud = "0";
+ parity = "N";
+ stop_bits = "1";
+ use_cts_rts = "0";
+ use_eop_register = "0";
+ sim_true_baud = "0";
+ sim_char_stream = "";
+ use_fifo = "0";
+ fifo_size = "16";
+ fifo_export_used = "0";
+ export_irq = "0";
+ hw_cts = "0";
+ trans_pin = "0";
+ fifo_size_tx = "8";
+ fifo_size_rx = "8";
+ tx_fifo_LE = "0";
+ rx_fifo_LE = "0";
+ combine_fifo = "0";
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Is_Enabled = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ Instantiate_In_System_Module = "1";
+ View
+ {
+ MESSAGES
+ {
+ }
+ Settings_Summary = "8-bit UART with 115200 baud, <br>
+ 1 stop bits and N parity";
+ }
+ }
+ SIMULATION
+ {
+ DISPLAY
+ {
+ SIGNAL a
+ {
+ name = " Bus Interface";
+ format = "Divider";
+ }
+ SIGNAL b
+ {
+ name = "chipselect";
+ }
+ SIGNAL c
+ {
+ name = "address";
+ radix = "hexadecimal";
+ }
+ SIGNAL d
+ {
+ name = "writedata";
+ radix = "hexadecimal";
+ }
+ SIGNAL e
+ {
+ name = "readdata";
+ radix = "hexadecimal";
+ }
+ SIGNAL f
+ {
+ name = " Internals";
+ format = "Divider";
+ }
+ SIGNAL g
+ {
+ name = "tx_ready";
+ }
+ SIGNAL h
+ {
+ name = "tx_data";
+ radix = "ascii";
+ }
+ SIGNAL i
+ {
+ name = "rx_char_ready";
+ }
+ SIGNAL j
+ {
+ name = "rx_data";
+ radix = "ascii";
+ }
+ }
+ INTERACTIVE_OUT log
+ {
+ enable = "0";
+ file = "_log_module.txt";
+ # suffix to $module_name in em_uart.pl
+ radix = "ascii";
+ signals = "temp,list";
+ exe = "perl -- tail-f.pl";
+ }
+ INTERACTIVE_IN drive
+ {
+ enable = "0";
+ # file descriptors are really just suffixes used by perl...
+ file = "_input_data_stream.dat";
+ mutex = "_input_data_mutex.dat";
+ log = "_in.log";
+ rate = "100";
+ signals = "temp,list";
+ exe = "perl -- uart.pl";
+ }
+ }
+ }
+ MODULE axonbus
+ {
+ SLAVE s1
+ {
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT irq
+ {
+ type = "irq";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT address
+ {
+ type = "address";
+ width = "3";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT begintransfer
+ {
+ type = "begintransfer";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT chipselect
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT read_n
+ {
+ type = "read_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT write_n
+ {
+ type = "write_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT writedata
+ {
+ type = "writedata";
+ width = "16";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT dataavailable
+ {
+ type = "dataavailable";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT readdata
+ {
+ type = "readdata";
+ width = "16";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT readyfordata
+ {
+ type = "readyfordata";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Has_IRQ = "1";
+ Bus_Type = "avalon";
+ Write_Wait_States = "1cycles";
+ Read_Wait_States = "1cycles";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "1";
+ Address_Alignment = "native";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Read_Latency = "0";
+ Is_Memory_Device = "0";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "16";
+ Address_Width = "3";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x07001140";
+ }
+ IRQ_MASTER cpu/data_master
+ {
+ IRQ_Number = "7";
+ }
+ Base_Address = "0x07001140";
+ Address_Group = "0";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT txd
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT rxd
+ {
+ type = "export";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT transmitting
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT rxused
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT txused
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT cts_n
+ {
+ type = "export";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "0";
+ }
+ PORT rts_n
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT irqexport
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ }
+ class = "fifoed_avalon_uart";
+ class_version = "7.1";
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ use_tx_fifo = "1";
+ use_rx_fifo = "1";
+ baud = "115200";
+ data_bits = "9";
+ fixed_baud = "1";
+ parity = "N";
+ stop_bits = "1";
+ use_cts_rts = "0";
+ use_eop_register = "0";
+ sim_true_baud = "0";
+ sim_char_stream = "";
+ use_fifo = "0";
+ fifo_size = "16";
+ fifo_export_used = "0";
+ export_irq = "0";
+ hw_cts = "0";
+ trans_pin = "1";
+ fifo_size_tx = "32";
+ fifo_size_rx = "32";
+ tx_fifo_LE = "0";
+ rx_fifo_LE = "0";
+ combine_fifo = "0";
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Is_Enabled = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ Instantiate_In_System_Module = "1";
+ View
+ {
+ MESSAGES
+ {
+ }
+ Settings_Summary = "9-bit UART with 115200 baud, <br>
+ 1 stop bits and N parity";
+ }
+ }
+ SIMULATION
+ {
+ DISPLAY
+ {
+ SIGNAL a
+ {
+ name = " Bus Interface";
+ format = "Divider";
+ }
+ SIGNAL b
+ {
+ name = "chipselect";
+ }
+ SIGNAL c
+ {
+ name = "address";
+ radix = "hexadecimal";
+ }
+ SIGNAL d
+ {
+ name = "writedata";
+ radix = "hexadecimal";
+ }
+ SIGNAL e
+ {
+ name = "readdata";
+ radix = "hexadecimal";
+ }
+ SIGNAL f
+ {
+ name = " Internals";
+ format = "Divider";
+ }
+ SIGNAL g
+ {
+ name = "tx_ready";
+ }
+ SIGNAL h
+ {
+ name = "tx_data";
+ radix = "ascii";
+ }
+ SIGNAL i
+ {
+ name = "rx_char_ready";
+ }
+ SIGNAL j
+ {
+ name = "rx_data";
+ radix = "ascii";
+ }
+ }
+ INTERACTIVE_OUT log
+ {
+ enable = "0";
+ file = "_log_module.txt";
+ # suffix to $module_name in em_uart.pl
+ radix = "ascii";
+ signals = "temp,list";
+ exe = "perl -- tail-f.pl";
+ }
+ INTERACTIVE_IN drive
+ {
+ enable = "0";
+ # file descriptors are really just suffixes used by perl...
+ file = "_input_data_stream.dat";
+ mutex = "_input_data_mutex.dat";
+ log = "_in.log";
+ rate = "100";
+ signals = "temp,list";
+ exe = "perl -- uart.pl";
+ }
+ }
+ }
+ MODULE I2C_local
+ {
+ SLAVE s1
+ {
+ PORT_WIRING
+ {
+ PORT csi_s1clk_clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT csi_s1clk_reset
+ {
+ type = "reset";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT ins_intout_irq
+ {
+ type = "irq";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT avs_s1_waitrequest_n
+ {
+ type = "waitrequest_n";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT avs_s1_writedata
+ {
+ type = "writedata";
+ width = "8";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT avs_s1_readdata
+ {
+ type = "readdata";
+ width = "8";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT avs_s1_chipselect
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT avs_s1_write
+ {
+ type = "write";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT avs_s1_address
+ {
+ type = "address";
+ width = "3";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Has_IRQ = "1";
+ Bus_Type = "avalon";
+ Read_Wait_States = "peripheral_controlled";
+ Write_Wait_States = "peripheral_controlled";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "native";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Read_Latency = "0";
+ Is_Memory_Device = "0";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "8";
+ Address_Width = "3";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x07001100";
+ }
+ IRQ_MASTER cpu/data_master
+ {
+ IRQ_Number = "1";
+ }
+ Base_Address = "0x07001100";
+ Address_Group = "0";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT coe_ext_export_scl
+ {
+ type = "export";
+ width = "1";
+ direction = "inout";
+ Is_Enabled = "1";
+ }
+ PORT coe_ext_export_sda
+ {
+ type = "export";
+ width = "1";
+ direction = "inout";
+ Is_Enabled = "1";
+ }
+ }
+ class = "no_legacy_module";
+ class_version = "7.080900";
+ gtf_class_name = "opencores_i2c_master";
+ gtf_class_version = "2.0";
+ SYSTEM_BUILDER_INFO
+ {
+ Do_Not_Generate = "1";
+ Instantiate_In_System_Module = "1";
+ Is_Bridge = "0";
+ Is_Enabled = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ View
+ {
+ MESSAGES
+ {
+ }
+ }
+ }
+ HDL_INFO
+ {
+ Simulation_HDL_Files = "/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_bit_ctrl.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_byte_ctrl.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_top.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/oc_i2c_master.vhd,/home/walter/VHDL/SYGEG1-080630/VHDL/Quartus_Altera/Prj/I2C_local.vhd";
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ terminated_ports
+ {
+ }
+ }
+ }
+ MODULE NIOS_clock_0
+ {
+ class = "altera_avalon_clock_adapter";
+ class_version = "7.080900";
+ SYSTEM_BUILDER_INFO
+ {
+ Is_Adapter = "1";
+ Rank_Order = "50";
+ Has_Clock = "0";
+ Is_Enabled = "1";
+ Instantiate_In_System_Module = "1";
+ Maximum_Pending_Read_Transactions_Multiplicand = "0";
+ View
+ {
+ Settings_Summary = "<i>altera_avalon_clock_adapter</i> is crossing 66.66MHz to 33.33MHz.";
+ MESSAGES
+ {
+ }
+ }
+ Clock_Source = "clk_half";
+ }
+ SLAVE in
+ {
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Clock_Source = "clk";
+ Has_IRQ = "0";
+ Read_Wait_States = "peripheral_controlled";
+ Write_Wait_States = "peripheral_controlled";
+ MASTERED_BY cpu/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x07010000";
+ }
+ Address_Alignment = "native";
+ Base_Address = "0x07010000";
+ Maximum_Pending_Read_Transactions = "0";
+ Address_Width = "8";
+ Data_Width = "32";
+ Maximum_Burst_Size = "1";
+ }
+ }
+ MASTER out
+ {
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Clock_Source = "clk_half";
+ Address_Width = "8";
+ Data_Width = "32";
+ Do_Stream_Reads = "0";
+ Do_Stream_Writes = "0";
+ Is_Readable = "1";
+ Maximum_Burst_Size = "1";
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ asp_debug = "0";
+ }
+ }
+}
--
1.6.0.4
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